| 596929b9 | 30-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
locks: linker variables to calculate per-cpu bakery lock size
This patch introduces explicit linker variables to mark the start and end of the per-cpu bakery lock section to help bakery_lock_normal.
locks: linker variables to calculate per-cpu bakery lock size
This patch introduces explicit linker variables to mark the start and end of the per-cpu bakery lock section to help bakery_lock_normal.c calculate the size of the section. This patch removes the previously used '__PERCPU_BAKERY_LOCK_SIZE__' linker variable to make the code uniform across GNU linker and ARM linker.
Change-Id: Ie0c51702cbc0fe8a2076005344a1fcebb48e7cca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 5e447816 | 01-Feb-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Remove unneeded include paths in PLAT_INCLUDES
Also, update platform_def.h guidelines about includes in the porting guide.
Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antoni
Remove unneeded include paths in PLAT_INCLUDES
Also, update platform_def.h guidelines about includes in the porting guide.
Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| bd9344f6 | 25-Jan-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
plat/arm: Sanitise includes
Use full include paths like it is done for common includes.
This cleanup was started in commit d40e0e08283a ("Sanitise includes across codebase"), but it only cleaned co
plat/arm: Sanitise includes
Use full include paths like it is done for common includes.
This cleanup was started in commit d40e0e08283a ("Sanitise includes across codebase"), but it only cleaned common files and drivers. This patch does the same to Arm platforms.
Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 09d40e0e | 14-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - inclu
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them).
For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems.
Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| c3cf06f1 | 08-Nov-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards.
The style that this proje
Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards.
The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H.
The exceptions are files that are imported from other projects:
- CryptoCell driver - dt-bindings folders - zlib headers
Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| a0fee747 | 31-Oct-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
context_mgmt: Fix MISRA defects
The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented().
Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: An
context_mgmt: Fix MISRA defects
The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented().
Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| a6238326 | 14-Sep-2018 |
John Tsichritzis <john.tsichritzis@arm.com> |
Replace S-EL3 references by EL3
The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix has been removed from wher
Replace S-EL3 references by EL3
The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix has been removed from wherever it was used as "S-EL3".
Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| b8424642 | 24-Sep-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
mediatek: Migrate to new interfaces
- mt6795: Migrate to new GIC interfaces. - Remove support for PSCI platform compatibility layer. - Migrate to bl31_early_platform_setup2(). - Migrate from cm_init
mediatek: Migrate to new interfaces
- mt6795: Migrate to new GIC interfaces. - Remove support for PSCI platform compatibility layer. - Migrate to bl31_early_platform_setup2(). - Migrate from cm_init_context() to cm_init_my_context(). - Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE. - Update Makefile paths. - Use private definition of bl31_params_t.
This is an incomplete migration, mt6795 doesn't currently compile.
Change-Id: Icf9307637066cd6f2166524715e4f117f5ce2350 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 1083b2b3 | 20-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org>
PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 30399885 | 12-Jul-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Fix types of arch.h definitions
Define the values as unsigned int or unsigned long long based on the actual size of the register. This prevents subtle issues caused by having a type that is too smal
Fix types of arch.h definitions
Define the values as unsigned int or unsigned long long based on the actual size of the register. This prevents subtle issues caused by having a type that is too small. For example:
#define OPTION_ENABLE 0x3 #define OPTION_SHIFT 32
uint64_t mask = OPTION_ENABLE << OPTION_SHIFT;
Because OPTION_ENABLE fits in an int, the value is considered an int. This means that, after shifting it 32 places to the left, the final result is 0. The correct way to define the values is:
#define OPTION_ENABLE ULL(0x3) #define OPTION_SHIFT U(32)
In this case, the compiler is forced to use a 64 bit value from the start, so shifting it 32 places to the left results in the expected value.
Change-Id: Ieaf2ffc2d8caa48c622db011f2aef549e713e019 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 5629b2b1 | 11-Apr-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Use ALIGN instead of NEXT in linker scripts
Clang linker doesn't support NEXT. As we are not using the MEMORY command to define discontinuous memory for the output file in any of the linker scripts,
Use ALIGN instead of NEXT in linker scripts
Clang linker doesn't support NEXT. As we are not using the MEMORY command to define discontinuous memory for the output file in any of the linker scripts, ALIGN and NEXT are equivalent.
Change-Id: I867ffb9c9a76d4e81c9ca7998280b2edf10efea0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 03364865 | 26-Apr-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Make TF UUID RFC 4122 compliant
RFC4122 defines that fields are stored in network order (big endian), but TF-A stores them in machine order (little endian by default in TF-A). We cannot change the f
Make TF UUID RFC 4122 compliant
RFC4122 defines that fields are stored in network order (big endian), but TF-A stores them in machine order (little endian by default in TF-A). We cannot change the future UUIDs that are already generated, but we can store all the bytes using arrays and modify fiptool to generate the UUIDs with the correct byte order.
Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 57d1e5fa | 18-Apr-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix pointer type mismatch of handlers
Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the typ
Fix pointer type mismatch of handlers
Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 6ab136c2 | 29-Mar-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements
Fix switch statements to comply with MISRA rules |
| 9f85f9e3 | 21-Mar-2018 |
Joel Hutton <Joel.Hutton@Arm.com> |
Clean usage of void pointers to access symbols
Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to ali
Clean usage of void pointers to access symbols
Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to aligned pointer values. To remove this restriction an IMPORT_SYM macro has been introduced, which declares it as a char pointer and casts it to the required type.
Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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| 649c48f5 | 14-Mar-2018 |
Jonathan Wright <jonathan.wright@arm.com> |
plat: fix switch statements to comply with MISRA rules
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7.
Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a75539162
plat: fix switch statements to comply with MISRA rules
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7.
Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
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| bd8e6a99 | 28-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1287 from davidcunado-arm/dc/fix_misra
Update ULL() macro and instances of ull to comply with MISRA |
| 5724481f | 16-Feb-2018 |
David Cunado <david.cunado@arm.com> |
Update ULL() macro and instances of ull to comply with MISRA
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.
This patch resolves this for the ULL() macro by usin
Update ULL() macro and instances of ull to comply with MISRA
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.
This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix.
Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
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| 883d1b5d | 23-Feb-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Add comments about mismatched TCR_ELx and xlat tables
When the MMU is enabled and the translation tables are mapped, data read/writes to the translation tables are made using the attributes specifie
Add comments about mismatched TCR_ELx and xlat tables
When the MMU is enabled and the translation tables are mapped, data read/writes to the translation tables are made using the attributes specified in the translation tables themselves. However, the MMU performs table walks with the attributes specified in TCR_ELx. They are completely independent, so special care has to be taken to make sure that they are the same.
This has to be done manually because it is not practical to have a test in the code. Such a test would need to know the virtual memory region that contains the translation tables and check that for all of the tables the attributes match the ones in TCR_ELx. As the tables may not even be mapped at all, this isn't a test that can be made generic.
The flags used by enable_mmu_xxx() have been moved to the same header where the functions are.
Also, some comments in the linker scripts related to the translation tables have been fixed.
Change-Id: I1754768bffdae75f53561b1c4a5baf043b45a304 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 383c8089 | 24-Jan-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Disable workaround for CVE-2017-5715 on unaffected platforms
Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> |
| 211d307c | 11-Dec-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1178 from davidcunado-arm/dc/enable_sve
Enable SVE for Non-secure world |
| 3872fc2d | 31-Oct-2017 |
David Cunado <david.cunado@arm.com> |
Do not enable SVE on pre-v8.2 platforms
Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero.
This
Do not enable SVE on pre-v8.2 platforms
Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero.
This has a minor performance improvement with no functional impact.
Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1 Signed-off-by: David Cunado <david.cunado@arm.com>
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| a2aedac2 | 15-Nov-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Replace magic numbers in linkerscripts by PAGE_SIZE
When defining different sections in linker scripts it is needed to align them to multiples of the page size. In most linker scripts this is done b
Replace magic numbers in linkerscripts by PAGE_SIZE
When defining different sections in linker scripts it is needed to align them to multiples of the page size. In most linker scripts this is done by aligning to the hardcoded value 4096 instead of PAGE_SIZE.
This may be confusing when taking a look at all the codebase, as 4096 is used in some parts that aren't meant to be a multiple of the page size.
Change-Id: I36c6f461c7782437a58d13d37ec8b822a1663ec1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 831b3752 | 29-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
mt8173: Migrate to using interrupt properties
Change-Id: I1463a4f9b74d74d59ac1d37b7b9c8e53416ab904 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
| ee1ebbd1 | 14-Jul-2017 |
Isla Mitchell <isla.mitchell@arm.com> |
Fix order of remaining platform #includes
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupi
Fix order of remaining platform #includes
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements.
Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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