1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <lib/cassert.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/arm/css/common/css_pm.h> 17 #include <plat/common/platform.h> 18 19 #include "../drivers/scp/css_scp.h" 20 21 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ 22 #pragma weak plat_arm_psci_pm_ops 23 24 #if ARM_RECOM_STATE_ID_ENC 25 /* 26 * The table storing the valid idle power states. Ensure that the 27 * array entries are populated in ascending order of state-id to 28 * enable us to use binary search during power state validation. 29 * The table must be terminated by a NULL entry. 30 */ 31 const unsigned int arm_pm_idle_states[] = { 32 /* State-id - 0x001 */ 33 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 34 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 35 /* State-id - 0x002 */ 36 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 37 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 38 /* State-id - 0x022 */ 39 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 40 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 41 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 42 /* State-id - 0x222 */ 43 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 44 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 45 #endif 46 0, 47 }; 48 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 49 50 /* 51 * All the power management helpers in this file assume at least cluster power 52 * level is supported. 53 */ 54 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, 55 assert_max_pwr_lvl_supported_mismatch); 56 57 /* 58 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL 59 * assumed by the CSS layer. 60 */ 61 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL, 62 assert_max_pwr_lvl_higher_than_css_sys_lvl); 63 64 /******************************************************************************* 65 * Handler called when a power domain is about to be turned on. The 66 * level and mpidr determine the affinity instance. 67 ******************************************************************************/ 68 int css_pwr_domain_on(u_register_t mpidr) 69 { 70 css_scp_on(mpidr); 71 72 return PSCI_E_SUCCESS; 73 } 74 75 static void css_pwr_domain_on_finisher_common( 76 const psci_power_state_t *target_state) 77 { 78 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 79 80 /* Enable the gic cpu interface */ 81 plat_arm_gic_cpuif_enable(); 82 83 /* 84 * Perform the common cluster specific operations i.e enable coherency 85 * if this cluster was off. 86 */ 87 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 88 plat_arm_interconnect_enter_coherency(); 89 } 90 91 /******************************************************************************* 92 * Handler called when a power level has just been powered on after 93 * being turned off earlier. The target_state encodes the low power state that 94 * each level has woken up from. This handler would never be invoked with 95 * the system power domain uninitialized as either the primary would have taken 96 * care of it as part of cold boot or the first core awakened from system 97 * suspend would have already initialized it. 98 ******************************************************************************/ 99 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 100 { 101 /* Assert that the system power domain need not be initialized */ 102 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 103 104 /* Program the gic per-cpu distributor or re-distributor interface */ 105 plat_arm_gic_pcpu_init(); 106 107 css_pwr_domain_on_finisher_common(target_state); 108 } 109 110 /******************************************************************************* 111 * Common function called while turning a cpu off or suspending it. It is called 112 * from css_off() or css_suspend() when these functions in turn are called for 113 * power domain at the highest power level which will be powered down. It 114 * performs the actions common to the OFF and SUSPEND calls. 115 ******************************************************************************/ 116 static void css_power_down_common(const psci_power_state_t *target_state) 117 { 118 /* Prevent interrupts from spuriously waking up this cpu */ 119 plat_arm_gic_cpuif_disable(); 120 121 /* Cluster is to be turned off, so disable coherency */ 122 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 123 plat_arm_interconnect_exit_coherency(); 124 } 125 126 /******************************************************************************* 127 * Handler called when a power domain is about to be turned off. The 128 * target_state encodes the power state that each level should transition to. 129 ******************************************************************************/ 130 void css_pwr_domain_off(const psci_power_state_t *target_state) 131 { 132 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 133 css_power_down_common(target_state); 134 css_scp_off(target_state); 135 } 136 137 /******************************************************************************* 138 * Handler called when a power domain is about to be suspended. The 139 * target_state encodes the power state that each level should transition to. 140 ******************************************************************************/ 141 void css_pwr_domain_suspend(const psci_power_state_t *target_state) 142 { 143 /* 144 * CSS currently supports retention only at cpu level. Just return 145 * as nothing is to be done for retention. 146 */ 147 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 148 return; 149 150 151 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 152 css_power_down_common(target_state); 153 154 /* Perform system domain state saving if issuing system suspend */ 155 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 156 arm_system_pwr_domain_save(); 157 158 /* Power off the Redistributor after having saved its context */ 159 plat_arm_gic_redistif_off(); 160 } 161 162 css_scp_suspend(target_state); 163 } 164 165 /******************************************************************************* 166 * Handler called when a power domain has just been powered on after 167 * having been suspended earlier. The target_state encodes the low power state 168 * that each level has woken up from. 169 * TODO: At the moment we reuse the on finisher and reinitialize the secure 170 * context. Need to implement a separate suspend finisher. 171 ******************************************************************************/ 172 void css_pwr_domain_suspend_finish( 173 const psci_power_state_t *target_state) 174 { 175 /* Return as nothing is to be done on waking up from retention. */ 176 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 177 return; 178 179 /* Perform system domain restore if woken up from system suspend */ 180 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) 181 /* 182 * At this point, the Distributor must be powered on to be ready 183 * to have its state restored. The Redistributor will be powered 184 * on as part of gicv3_rdistif_init_restore. 185 */ 186 arm_system_pwr_domain_resume(); 187 188 css_pwr_domain_on_finisher_common(target_state); 189 } 190 191 /******************************************************************************* 192 * Handlers to shutdown/reboot the system 193 ******************************************************************************/ 194 void __dead2 css_system_off(void) 195 { 196 css_scp_sys_shutdown(); 197 } 198 199 void __dead2 css_system_reset(void) 200 { 201 css_scp_sys_reboot(); 202 } 203 204 /******************************************************************************* 205 * Handler called when the CPU power domain is about to enter standby. 206 ******************************************************************************/ 207 void css_cpu_standby(plat_local_state_t cpu_state) 208 { 209 unsigned int scr; 210 211 assert(cpu_state == ARM_LOCAL_STATE_RET); 212 213 scr = read_scr_el3(); 214 /* 215 * Enable the Non secure interrupt to wake the CPU. 216 * In GICv3 affinity routing mode, the non secure group1 interrupts use 217 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. 218 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 219 * routing mode. 220 */ 221 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 222 isb(); 223 dsb(); 224 wfi(); 225 226 /* 227 * Restore SCR to the original value, synchronisation of scr_el3 is 228 * done by eret while el3_exit to save some execution cycles. 229 */ 230 write_scr_el3(scr); 231 } 232 233 /******************************************************************************* 234 * Handler called to return the 'req_state' for system suspend. 235 ******************************************************************************/ 236 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) 237 { 238 unsigned int i; 239 240 /* 241 * System Suspend is supported only if the system power domain node 242 * is implemented. 243 */ 244 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); 245 246 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 247 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 248 } 249 250 /******************************************************************************* 251 * Handler to query CPU/cluster power states from SCP 252 ******************************************************************************/ 253 int css_node_hw_state(u_register_t mpidr, unsigned int power_level) 254 { 255 return css_scp_get_power_state(mpidr, power_level); 256 } 257 258 /* 259 * The system power domain suspend is only supported only via 260 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 261 * will be downgraded to the lower level. 262 */ 263 static int css_validate_power_state(unsigned int power_state, 264 psci_power_state_t *req_state) 265 { 266 int rc; 267 rc = arm_validate_power_state(power_state, req_state); 268 269 /* 270 * Ensure that we don't overrun the pwr_domain_state array in the case 271 * where the platform supported max power level is less than the system 272 * power level 273 */ 274 275 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) 276 277 /* 278 * Ensure that the system power domain level is never suspended 279 * via PSCI CPU SUSPEND API. Currently system suspend is only 280 * supported via PSCI SYSTEM SUSPEND API. 281 */ 282 283 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = 284 ARM_LOCAL_STATE_RUN; 285 #endif 286 287 return rc; 288 } 289 290 /* 291 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the 292 * `css_validate_power_state`, we do not downgrade the system power 293 * domain level request in `power_state` as it will be used to query the 294 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 295 */ 296 static int css_translate_power_state_by_mpidr(u_register_t mpidr, 297 unsigned int power_state, 298 psci_power_state_t *output_state) 299 { 300 return arm_validate_power_state(power_state, output_state); 301 } 302 303 /******************************************************************************* 304 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 305 * platform will take care of registering the handlers with PSCI. 306 ******************************************************************************/ 307 plat_psci_ops_t plat_arm_psci_pm_ops = { 308 .pwr_domain_on = css_pwr_domain_on, 309 .pwr_domain_on_finish = css_pwr_domain_on_finish, 310 .pwr_domain_off = css_pwr_domain_off, 311 .cpu_standby = css_cpu_standby, 312 .pwr_domain_suspend = css_pwr_domain_suspend, 313 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 314 .system_off = css_system_off, 315 .system_reset = css_system_reset, 316 .validate_power_state = css_validate_power_state, 317 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 318 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr, 319 .get_node_hw_state = css_node_hw_state, 320 .get_sys_suspend_power_state = css_get_sys_suspend_power_state, 321 322 #if defined(PLAT_ARM_MEM_PROT_ADDR) 323 .mem_protect_chk = arm_psci_mem_protect_chk, 324 .read_mem_protect = arm_psci_read_mem_protect, 325 .write_mem_protect = arm_nor_psci_write_mem_protect, 326 #endif 327 #if CSS_USE_SCMI_SDS_DRIVER 328 .system_reset2 = css_system_reset2, 329 #endif 330 }; 331