1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && (RESET_TO_BL31 || (ENABLE_SPM && !SPM_MM)) 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 #include <drivers/arm/tzc400.h> 22 #include <lib/utils_def.h> 23 #include <plat/arm/board/common/v2m_def.h> 24 #include <plat/arm/common/arm_def.h> 25 #include <plat/arm/common/arm_spm_def.h> 26 #include <plat/common/common_def.h> 27 28 #include "../fvp_def.h" 29 30 /* Required platform porting definitions */ 31 #define PLATFORM_CORE_COUNT \ 32 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 33 34 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 35 PLATFORM_CORE_COUNT) + 1 36 37 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 38 39 /* 40 * Other platform porting definitions are provided by included headers 41 */ 42 43 /* 44 * Required ARM standard platform porting definitions 45 */ 46 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 47 48 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 49 50 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 51 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 52 53 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 54 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 55 56 /* virtual address used by dynamic mem_protect for chunk_base */ 57 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 58 59 /* No SCP in FVP */ 60 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 61 62 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 63 64 /* 65 * Load address of BL33 for this platform port 66 */ 67 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) 68 69 /* 70 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 71 * plat_arm_mmap array defined for each BL stage. 72 */ 73 #if defined(IMAGE_BL31) 74 # if ENABLE_SPM 75 # define PLAT_ARM_MMAP_ENTRIES 9 76 # define MAX_XLAT_TABLES 9 77 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 78 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 79 # else 80 # define PLAT_ARM_MMAP_ENTRIES 8 81 # define MAX_XLAT_TABLES 5 82 # endif 83 #elif defined(IMAGE_BL32) 84 # define PLAT_ARM_MMAP_ENTRIES 8 85 # define MAX_XLAT_TABLES 5 86 #elif !USE_ROMLIB 87 # define PLAT_ARM_MMAP_ENTRIES 11 88 # define MAX_XLAT_TABLES 5 89 #else 90 # define PLAT_ARM_MMAP_ENTRIES 12 91 # define MAX_XLAT_TABLES 6 92 #endif 93 94 /* 95 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 96 * plus a little space for growth. 97 */ 98 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 99 100 /* 101 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 102 */ 103 104 #if USE_ROMLIB 105 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 106 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 107 #else 108 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 109 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 110 #endif 111 112 /* 113 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 114 * little space for growth. 115 */ 116 #if TRUSTED_BOARD_BOOT 117 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 118 #else 119 # define PLAT_ARM_MAX_BL2_SIZE UL(0x11000) 120 #endif 121 122 /* 123 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 124 * calculated using the current BL31 PROGBITS debug size plus the sizes of 125 * BL2 and BL1-RW 126 */ 127 #if ENABLE_SPM && !SPM_MM 128 #define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) 129 #else 130 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 131 #endif 132 133 #ifdef AARCH32 134 /* 135 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 136 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 137 * BL2 and BL1-RW 138 */ 139 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 140 #endif 141 142 /* 143 * Size of cacheable stacks 144 */ 145 #if defined(IMAGE_BL1) 146 # if TRUSTED_BOARD_BOOT 147 # define PLATFORM_STACK_SIZE UL(0x1000) 148 # else 149 # define PLATFORM_STACK_SIZE UL(0x440) 150 # endif 151 #elif defined(IMAGE_BL2) 152 # if TRUSTED_BOARD_BOOT 153 # define PLATFORM_STACK_SIZE UL(0x1000) 154 # else 155 # define PLATFORM_STACK_SIZE UL(0x400) 156 # endif 157 #elif defined(IMAGE_BL2U) 158 # define PLATFORM_STACK_SIZE UL(0x400) 159 #elif defined(IMAGE_BL31) 160 # if ENABLE_SPM 161 # define PLATFORM_STACK_SIZE UL(0x600) 162 # elif PLAT_XLAT_TABLES_DYNAMIC 163 # define PLATFORM_STACK_SIZE UL(0x800) 164 # else 165 # define PLATFORM_STACK_SIZE UL(0x400) 166 # endif 167 #elif defined(IMAGE_BL32) 168 # define PLATFORM_STACK_SIZE UL(0x440) 169 #endif 170 171 #define MAX_IO_DEVICES 3 172 #define MAX_IO_HANDLES 4 173 174 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 175 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 176 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 177 178 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 179 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 180 181 /* 182 * PL011 related constants 183 */ 184 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 185 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 186 187 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 188 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 189 190 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 191 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 192 193 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 194 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 195 196 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 197 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 198 199 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 200 201 /* CCI related constants */ 202 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 203 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 204 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 205 206 /* CCI-500/CCI-550 on Base platform */ 207 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 208 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 209 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 210 211 /* CCN related constants. Only CCN 502 is currently supported */ 212 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 213 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 214 215 /* System timer related constants */ 216 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 217 218 /* Mailbox base address */ 219 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 220 221 222 /* TrustZone controller related constants 223 * 224 * Currently only filters 0 and 2 are connected on Base FVP. 225 * Filter 0 : CPU clusters (no access to DRAM by default) 226 * Filter 1 : not connected 227 * Filter 2 : LCDs (access to VRAM allowed by default) 228 * Filter 3 : not connected 229 * Programming unconnected filters will have no effect at the 230 * moment. These filter could, however, be connected in future. 231 * So care should be taken not to configure the unused filters. 232 * 233 * Allow only non-secure access to all DRAM to supported devices. 234 * Give access to the CPUs and Virtio. Some devices 235 * would normally use the default ID so allow that too. 236 */ 237 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 238 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 239 240 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 241 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 242 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 243 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 244 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 245 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 246 247 /* 248 * GIC related constants to cater for both GICv2 and GICv3 instances of an 249 * FVP. They could be overriden at runtime in case the FVP implements the legacy 250 * VE memory map. 251 */ 252 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 253 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 254 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 255 256 /* 257 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 258 * terminology. On a GICv2 system or mode, the lists will be merged and treated 259 * as Group 0 interrupts. 260 */ 261 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 262 ARM_G1S_IRQ_PROPS(grp), \ 263 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 264 GIC_INTR_CFG_LEVEL), \ 265 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 266 GIC_INTR_CFG_LEVEL) 267 268 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 269 270 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 271 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 272 273 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 274 PLAT_SP_IMAGE_NS_BUF_SIZE) 275 276 #define PLAT_SP_PRI PLAT_RAS_PRI 277 278 #endif /* PLATFORM_DEF_H */ 279