xlat: Make function to calculate TCR PA bits public

This function can be useful to setup TCR_ELx by callers that don't use
the translation tables library to setup the system registers related
to the

xlat: Make function to calculate TCR PA bits public

This function can be useful to setup TCR_ELx by callers that don't use
the translation tables library to setup the system registers related
to them. By making it common, it can be reused whenever it is needed
without duplicating code.

Change-Id: Ibfada9e846d2a6cd113b1925ac911bb27327d375
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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aarch32: add missing dmb() macro

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

ARMv7 may not support Virtualization Extensions

ARMv7-A Virtualization extensions brings new instructions and resources
that were supported by later architectures. Reference ARM ARM Issue C.c
[DDI04

ARMv7 may not support Virtualization Extensions

ARMv7-A Virtualization extensions brings new instructions and resources
that were supported by later architectures. Reference ARM ARM Issue C.c
[DDI0406C_C].

ERET and extended MSR/MRS instructions, as specified in [DDI0406C_C] in
ID_PFR1 description of bits[15:12] (Virtualization Extensions):
A value of 0b0001 implies implementation of the HVC, ERET, MRS
(Banked register), and MSR (Banked register) instructions. The ID_ISARs
do not identify whether these instructions are implemented.

UDIV/SDIV were introduced with the Virtualization extensions, even if
not strictly related to the virtualization extensions.

If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform
shall define ARMV7_SUPPORTS_VIRTUALIZATION to enable virtualization
extension related resources.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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ARMv7: introduce Cortex-A12

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

ARMv7: introduce Cortex-A17

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

ARMv7: introduce Cortex-A7

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

ARMv7: introduce Cortex-A5

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

ARMv7: introduce Cortex-A9

As Cortex-A9 needs to manually enable program flow prediction,
do not reset SCTLR[Z] at entry. Platform should enable it only
once MMU is enabled.

Change-Id: I34e1ee2da73

ARMv7: introduce Cortex-A9

As Cortex-A9 needs to manually enable program flow prediction,
do not reset SCTLR[Z] at entry. Platform should enable it only
once MMU is enabled.

Change-Id: I34e1ee2da73221903f7767f23bc6fc10ad01e3de
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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ARMv7: introduce Cortex-A15

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

ARMv7 architecture have specific system registers

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

Merge pull request #1153 from robertovargas-arm/fix-macros

Avoid use of undefined macros

Merge pull request #1151 from JoelHutton/jh/MISRA-Mandatory

Change sizeof to use type of struct not function

Fix usage of IMAGE_BLx macros

These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on be

Fix usage of IMAGE_BLx macros

These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on being 0 by default.

Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Change sizeof to use type of struct not function

Change sizeof call so it references a static type instead of return of
a function in order to be MISRA compliant.

Change-Id: I6f1adb206073d6cd200156

Change sizeof to use type of struct not function

Change sizeof call so it references a static type instead of return of
a function in order to be MISRA compliant.

Change-Id: I6f1adb206073d6cd200156e281b8d76249e3af0e
Signed-off-by: Joel Hutton <joel.hutton@arm.com>

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aarch64: Add PubSub events to capture security state transitions

Add events that trigger before entry to normal/secure world. The
events trigger after the normal/secure context has been restored.

aarch64: Add PubSub events to capture security state transitions

Add events that trigger before entry to normal/secure world. The
events trigger after the normal/secure context has been restored.

Similarly add events that trigger after leaving normal/secure world.
The events trigger after the normal/secure context has been saved.

Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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PSCI: Publish CPU ON event

This allows other EL3 components to subscribe to CPU on events.

Update Firmware Design guide to list psci_cpu_on_finish as an available
event.

Change-Id: Ida774afe0f9cdc

PSCI: Publish CPU ON event

This allows other EL3 components to subscribe to CPU on events.

Update Firmware Design guide to list psci_cpu_on_finish as an available
event.

Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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BL31: Introduce Publish and Subscribe framework

This light-weight framework enables some EL3 components to publish
events which other EL3 components can subscribe to. Publisher can
optionally pass o

BL31: Introduce Publish and Subscribe framework

This light-weight framework enables some EL3 components to publish
events which other EL3 components can subscribe to. Publisher can
optionally pass opaque data for subscribers. The order in which
subscribers are called is not defined.

Firmware design updated.

Change-Id: I24a3a70b2b1dedcb1f73cf48313818aebf75ebb6
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Merge pull request #1130 from jeenu-arm/gic-patches

New GIC APIs and specifying interrupt propertes

Merge pull request #1136 from antonio-nino-diaz-arm/an/xlat-get-set-attr

Add APIs to get and modify attributes of memory regions

Merge pull request #1129 from robertovargas-arm/enable_O0

Fix use of MSR (immediate)

Merge pull request #1127 from davidcunado-arm/dc/pmrc_init

Init and save / restore of PMCR_EL0 / PMCR

Merge pull request #1126 from robertovargas-arm/psci-v1.1

Update PSCI to v1.1

Introduce functions to disable the MMU in EL1

The implementation is the same as those used to disable it in EL3.

Change-Id: Ibfe7e69034a691fbf57477c5a76a8cdca28f6b26
Signed-off-by: Antonio Nino Dia

Introduce functions to disable the MMU in EL1

The implementation is the same as those used to disable it in EL3.

Change-Id: Ibfe7e69034a691fbf57477c5a76a8cdca28f6b26
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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xlat: Introduce API to change memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to change the memory attributes of a memory
region. It

xlat: Introduce API to change memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to change the memory attributes of a memory
region. It may be used to change its execution permissions and
data access permissions.

As a prerequisite, the memory must be already mapped. Moreover, it
must be mapped at the finest granularity (currently 4 KB).

Change-Id: I242a8c6f0f3ef2b0a81a61e28706540462faca3c
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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xlat: Introduce API to get memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to query the memory attributes of a memory block
or a mem

xlat: Introduce API to get memory attributes of a region

This patch introduces a new API in the translation tables library
(v2), that allows to query the memory attributes of a memory block
or a memory page.

Change-Id: I45a8b39a53da39e7617cbac4bff5658dc1b20a11
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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