1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <interrupt_mgmt.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <smcc_helpers.h> 17 #include <string.h> 18 #include <utils.h> 19 20 21 /******************************************************************************* 22 * Context management library initialisation routine. This library is used by 23 * runtime services to share pointers to 'cpu_context' structures for the secure 24 * and non-secure states. Management of the structures and their associated 25 * memory is not done by the context management library e.g. the PSCI service 26 * manages the cpu context used for entry from and exit to the non-secure state. 27 * The Secure payload dispatcher service manages the context(s) corresponding to 28 * the secure state. It also uses this library to get access to the non-secure 29 * state cpu context pointers. 30 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 31 * which will used for programming an entry into a lower EL. The same context 32 * will used to save state upon exception entry from that EL. 33 ******************************************************************************/ 34 void cm_init(void) 35 { 36 /* 37 * The context management library has only global data to intialize, but 38 * that will be done when the BSS is zeroed out 39 */ 40 } 41 42 /******************************************************************************* 43 * The following function initializes the cpu_context 'ctx' for 44 * first use, and sets the initial entrypoint state as specified by the 45 * entry_point_info structure. 46 * 47 * The security state to initialize is determined by the SECURE attribute 48 * of the entry_point_info. The function returns a pointer to the initialized 49 * context and sets this as the next context to return to. 50 * 51 * The EE and ST attributes are used to configure the endianess and secure 52 * timer availability for the new execution context. 53 * 54 * To prepare the register state for entry call cm_prepare_el3_exit() and 55 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 56 * cm_e1_sysreg_context_restore(). 57 ******************************************************************************/ 58 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 59 { 60 unsigned int security_state; 61 uint32_t scr_el3; 62 el3_state_t *state; 63 gp_regs_t *gp_regs; 64 unsigned long sctlr_elx; 65 66 assert(ctx); 67 68 security_state = GET_SECURITY_STATE(ep->h.attr); 69 70 /* Clear any residual register values from the context */ 71 zeromem(ctx, sizeof(*ctx)); 72 73 /* 74 * Base the context SCR on the current value, adjust for entry point 75 * specific requirements and set trap bits from the IMF 76 * TODO: provide the base/global SCR bits using another mechanism? 77 */ 78 scr_el3 = read_scr(); 79 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 80 SCR_ST_BIT | SCR_HCE_BIT); 81 82 if (security_state != SECURE) 83 scr_el3 |= SCR_NS_BIT; 84 85 if (GET_RW(ep->spsr) == MODE_RW_64) 86 scr_el3 |= SCR_RW_BIT; 87 88 if (EP_GET_ST(ep->h.attr)) 89 scr_el3 |= SCR_ST_BIT; 90 91 #ifndef HANDLE_EA_EL3_FIRST 92 /* Explicitly stop to trap aborts from lower exception levels. */ 93 scr_el3 &= ~SCR_EA_BIT; 94 #endif 95 96 #ifdef IMAGE_BL31 97 /* 98 * IRQ/FIQ bits only need setting if interrupt routing 99 * model has been set up for BL31. 100 */ 101 scr_el3 |= get_scr_el3_from_routing_model(security_state); 102 #endif 103 104 /* 105 * Set up SCTLR_ELx for the target exception level: 106 * EE bit is taken from the entrypoint attributes 107 * M, C and I bits must be zero (as required by PSCI specification) 108 * 109 * The target exception level is based on the spsr mode requested. 110 * If execution is requested to EL2 or hyp mode, HVC is enabled 111 * via SCR_EL3.HCE. 112 * 113 * Always compute the SCTLR_EL1 value and save in the cpu_context 114 * - the EL2 registers are set up by cm_preapre_ns_entry() as they 115 * are not part of the stored cpu_context 116 * 117 * TODO: In debug builds the spsr should be validated and checked 118 * against the CPU support, security state, endianess and pc 119 */ 120 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 121 if (GET_RW(ep->spsr) == MODE_RW_64) 122 sctlr_elx |= SCTLR_EL1_RES1; 123 else { 124 sctlr_elx |= SCTLR_AARCH32_EL1_RES1; 125 /* 126 * If lower non-secure EL is AArch32, enable the CP15BEN, nTWI 127 * & nTWI bits. This aligns with SCTLR initialization on 128 * systems with an AArch32 EL3, where these bits 129 * architecturally reset to 1. 130 */ 131 if (security_state != SECURE) 132 sctlr_elx |= SCTLR_CP15BEN_BIT | SCTLR_NTWI_BIT 133 | SCTLR_NTWE_BIT; 134 } 135 136 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 137 138 if ((GET_RW(ep->spsr) == MODE_RW_64 139 && GET_EL(ep->spsr) == MODE_EL2) 140 || (GET_RW(ep->spsr) != MODE_RW_64 141 && GET_M32(ep->spsr) == MODE32_hyp)) { 142 scr_el3 |= SCR_HCE_BIT; 143 } 144 145 /* Populate EL3 state so that we've the right context before doing ERET */ 146 state = get_el3state_ctx(ctx); 147 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 148 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 149 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 150 151 /* 152 * Store the X0-X7 value from the entrypoint into the context 153 * Use memcpy as we are in control of the layout of the structures 154 */ 155 gp_regs = get_gpregs_ctx(ctx); 156 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 157 } 158 159 /******************************************************************************* 160 * The following function initializes the cpu_context for a CPU specified by 161 * its `cpu_idx` for first use, and sets the initial entrypoint state as 162 * specified by the entry_point_info structure. 163 ******************************************************************************/ 164 void cm_init_context_by_index(unsigned int cpu_idx, 165 const entry_point_info_t *ep) 166 { 167 cpu_context_t *ctx; 168 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 169 cm_init_context_common(ctx, ep); 170 } 171 172 /******************************************************************************* 173 * The following function initializes the cpu_context for the current CPU 174 * for first use, and sets the initial entrypoint state as specified by the 175 * entry_point_info structure. 176 ******************************************************************************/ 177 void cm_init_my_context(const entry_point_info_t *ep) 178 { 179 cpu_context_t *ctx; 180 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 181 cm_init_context_common(ctx, ep); 182 } 183 184 /******************************************************************************* 185 * Prepare the CPU system registers for first entry into secure or normal world 186 * 187 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 188 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 189 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 190 * For all entries, the EL1 registers are initialized from the cpu_context 191 ******************************************************************************/ 192 void cm_prepare_el3_exit(uint32_t security_state) 193 { 194 uint32_t sctlr_elx, scr_el3, cptr_el2; 195 cpu_context_t *ctx = cm_get_context(security_state); 196 197 assert(ctx); 198 199 if (security_state == NON_SECURE) { 200 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 201 if (scr_el3 & SCR_HCE_BIT) { 202 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 203 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 204 CTX_SCTLR_EL1); 205 sctlr_elx &= ~SCTLR_EE_BIT; 206 sctlr_elx |= SCTLR_EL2_RES1; 207 write_sctlr_el2(sctlr_elx); 208 } else if (EL_IMPLEMENTED(2)) { 209 /* EL2 present but unused, need to disable safely */ 210 211 /* HCR_EL2 = 0, except RW bit set to match SCR_EL3 */ 212 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); 213 214 /* SCTLR_EL2 : can be ignored when bypassing */ 215 216 /* CPTR_EL2 : disable all traps TCPAC, TTA, TFP */ 217 cptr_el2 = read_cptr_el2(); 218 cptr_el2 &= ~(TCPAC_BIT | TTA_BIT | TFP_BIT); 219 write_cptr_el2(cptr_el2); 220 221 /* Enable EL1 access to timer */ 222 write_cnthctl_el2(EL1PCEN_BIT | EL1PCTEN_BIT); 223 224 /* Reset CNTVOFF_EL2 */ 225 write_cntvoff_el2(0); 226 227 /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ 228 write_vpidr_el2(read_midr_el1()); 229 write_vmpidr_el2(read_mpidr_el1()); 230 231 /* 232 * Reset VTTBR_EL2. 233 * Needed because cache maintenance operations depend on 234 * the VMID even when non-secure EL1&0 stage 2 address 235 * translation are disabled. 236 */ 237 write_vttbr_el2(0); 238 /* 239 * Avoid unexpected debug traps in case where MDCR_EL2 240 * is not completely reset by the hardware - set 241 * MDCR_EL2.HPMN to PMCR_EL0.N and zero the remaining 242 * bits. 243 * MDCR_EL2.HPMN and PMCR_EL0.N fields are the same size 244 * (5 bits) and HPMN is at offset zero within MDCR_EL2. 245 */ 246 write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS) 247 >> PMCR_EL0_N_SHIFT); 248 /* 249 * Avoid unexpected traps of non-secure access to 250 * certain system registers at EL1 or lower where 251 * HSTR_EL2 is not completely reset to zero by the 252 * hardware - zero the entire register. 253 */ 254 write_hstr_el2(0); 255 /* 256 * Reset CNTHP_CTL_EL2 to disable the EL2 physical timer 257 * and therefore prevent timer interrupts. 258 */ 259 write_cnthp_ctl_el2(0); 260 } 261 } 262 263 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 264 265 cm_set_next_context(ctx); 266 } 267 268 /******************************************************************************* 269 * The next four functions are used by runtime services to save and restore 270 * EL1 context on the 'cpu_context' structure for the specified security 271 * state. 272 ******************************************************************************/ 273 void cm_el1_sysregs_context_save(uint32_t security_state) 274 { 275 cpu_context_t *ctx; 276 277 ctx = cm_get_context(security_state); 278 assert(ctx); 279 280 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 281 } 282 283 void cm_el1_sysregs_context_restore(uint32_t security_state) 284 { 285 cpu_context_t *ctx; 286 287 ctx = cm_get_context(security_state); 288 assert(ctx); 289 290 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 291 } 292 293 /******************************************************************************* 294 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 295 * given security state with the given entrypoint 296 ******************************************************************************/ 297 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 298 { 299 cpu_context_t *ctx; 300 el3_state_t *state; 301 302 ctx = cm_get_context(security_state); 303 assert(ctx); 304 305 /* Populate EL3 state so that ERET jumps to the correct entry */ 306 state = get_el3state_ctx(ctx); 307 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 308 } 309 310 /******************************************************************************* 311 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 312 * pertaining to the given security state 313 ******************************************************************************/ 314 void cm_set_elr_spsr_el3(uint32_t security_state, 315 uintptr_t entrypoint, uint32_t spsr) 316 { 317 cpu_context_t *ctx; 318 el3_state_t *state; 319 320 ctx = cm_get_context(security_state); 321 assert(ctx); 322 323 /* Populate EL3 state so that ERET jumps to the correct entry */ 324 state = get_el3state_ctx(ctx); 325 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 326 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 327 } 328 329 /******************************************************************************* 330 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 331 * pertaining to the given security state using the value and bit position 332 * specified in the parameters. It preserves all other bits. 333 ******************************************************************************/ 334 void cm_write_scr_el3_bit(uint32_t security_state, 335 uint32_t bit_pos, 336 uint32_t value) 337 { 338 cpu_context_t *ctx; 339 el3_state_t *state; 340 uint32_t scr_el3; 341 342 ctx = cm_get_context(security_state); 343 assert(ctx); 344 345 /* Ensure that the bit position is a valid one */ 346 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 347 348 /* Ensure that the 'value' is only a bit wide */ 349 assert(value <= 1); 350 351 /* 352 * Get the SCR_EL3 value from the cpu context, clear the desired bit 353 * and set it to its new value. 354 */ 355 state = get_el3state_ctx(ctx); 356 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 357 scr_el3 &= ~(1 << bit_pos); 358 scr_el3 |= value << bit_pos; 359 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 360 } 361 362 /******************************************************************************* 363 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 364 * given security state. 365 ******************************************************************************/ 366 uint32_t cm_get_scr_el3(uint32_t security_state) 367 { 368 cpu_context_t *ctx; 369 el3_state_t *state; 370 371 ctx = cm_get_context(security_state); 372 assert(ctx); 373 374 /* Populate EL3 state so that ERET jumps to the correct entry */ 375 state = get_el3state_ctx(ctx); 376 return read_ctx_reg(state, CTX_SCR_EL3); 377 } 378 379 /******************************************************************************* 380 * This function is used to program the context that's used for exception 381 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 382 * the required security state 383 ******************************************************************************/ 384 void cm_set_next_eret_context(uint32_t security_state) 385 { 386 cpu_context_t *ctx; 387 388 ctx = cm_get_context(security_state); 389 assert(ctx); 390 391 cm_set_next_context(ctx); 392 } 393