1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <cassert.h> 35 #include <platform_def.h> 36 #include <utils.h> 37 #include <xlat_tables_v2.h> 38 #include "../xlat_tables_private.h" 39 40 #if ENABLE_ASSERTIONS 41 static unsigned long long xlat_arch_get_max_supported_pa(void) 42 { 43 /* Physical address space size for long descriptor format. */ 44 return (1ull << 40) - 1ull; 45 } 46 #endif /* ENABLE_ASSERTIONS*/ 47 48 int is_mmu_enabled(void) 49 { 50 return (read_sctlr() & SCTLR_M_BIT) != 0; 51 } 52 53 #if PLAT_XLAT_TABLES_DYNAMIC 54 55 void xlat_arch_tlbi_va(uintptr_t va) 56 { 57 /* 58 * Ensure the translation table write has drained into memory before 59 * invalidating the TLB entry. 60 */ 61 dsbishst(); 62 63 tlbimvaais(TLBI_ADDR(va)); 64 } 65 66 void xlat_arch_tlbi_va_sync(void) 67 { 68 /* Invalidate all entries from branch predictors. */ 69 bpiallis(); 70 71 /* 72 * A TLB maintenance instruction can complete at any time after 73 * it is issued, but is only guaranteed to be complete after the 74 * execution of DSB by the PE that executed the TLB maintenance 75 * instruction. After the TLB invalidate instruction is 76 * complete, no new memory accesses using the invalidated TLB 77 * entries will be observed by any observer of the system 78 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 79 * "Ordering and completion of TLB maintenance instructions". 80 */ 81 dsbish(); 82 83 /* 84 * The effects of a completed TLB maintenance instruction are 85 * only guaranteed to be visible on the PE that executed the 86 * instruction after the execution of an ISB instruction by the 87 * PE that executed the TLB maintenance instruction. 88 */ 89 isb(); 90 } 91 92 #endif /* PLAT_XLAT_TABLES_DYNAMIC */ 93 94 int xlat_arch_current_el(void) 95 { 96 /* 97 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 98 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 99 */ 100 return 3; 101 } 102 103 uint64_t xlat_arch_get_xn_desc(int el __unused) 104 { 105 return UPPER_ATTRS(XN); 106 } 107 108 void init_xlat_tables_arch(unsigned long long max_pa) 109 { 110 assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= 111 xlat_arch_get_max_supported_pa()); 112 } 113 114 /******************************************************************************* 115 * Function for enabling the MMU in Secure PL1, assuming that the 116 * page-tables have already been created. 117 ******************************************************************************/ 118 void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table) 119 120 { 121 u_register_t mair0, ttbcr, sctlr; 122 uint64_t ttbr0; 123 124 assert(IS_IN_SECURE()); 125 assert((read_sctlr() & SCTLR_M_BIT) == 0); 126 127 /* Invalidate TLBs at the current exception level */ 128 tlbiall(); 129 130 /* Set attributes in the right indices of the MAIR */ 131 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 132 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 133 ATTR_IWBWA_OWBWA_NTR_INDEX); 134 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 135 ATTR_NON_CACHEABLE_INDEX); 136 write_mair0(mair0); 137 138 /* 139 * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1. 140 */ 141 if (flags & XLAT_TABLE_NC) { 142 /* Inner & outer non-cacheable non-shareable. */ 143 ttbcr = TTBCR_EAE_BIT | 144 TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 145 TTBCR_RGN0_INNER_NC | 146 (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); 147 } else { 148 /* Inner & outer WBWA & shareable. */ 149 ttbcr = TTBCR_EAE_BIT | 150 TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 151 TTBCR_RGN0_INNER_WBA | 152 (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); 153 } 154 ttbcr |= TTBCR_EPD1_BIT; 155 write_ttbcr(ttbcr); 156 157 /* Set TTBR0 bits as well */ 158 ttbr0 = (uint64_t)(uintptr_t) base_table; 159 write64_ttbr0(ttbr0); 160 write64_ttbr1(0); 161 162 /* 163 * Ensure all translation table writes have drained 164 * into memory, the TLB invalidation is complete, 165 * and translation register writes are committed 166 * before enabling the MMU 167 */ 168 dsb(); 169 isb(); 170 171 sctlr = read_sctlr(); 172 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 173 174 if (flags & DISABLE_DCACHE) 175 sctlr &= ~SCTLR_C_BIT; 176 else 177 sctlr |= SCTLR_C_BIT; 178 179 write_sctlr(sctlr); 180 181 /* Ensure the MMU enable takes effect immediately */ 182 isb(); 183 } 184 185 void enable_mmu_arch(unsigned int flags, uint64_t *base_table) 186 { 187 enable_mmu_internal_secure(flags, base_table); 188 } 189