1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <cpu_data.h> 14 #include <debug.h> 15 #include <platform.h> 16 #include <pmf.h> 17 #include <runtime_instr.h> 18 #include <stddef.h> 19 #include "psci_private.h" 20 21 /******************************************************************************* 22 * This function does generic and platform specific operations after a wake-up 23 * from standby/retention states at multiple power levels. 24 ******************************************************************************/ 25 static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, 26 unsigned int end_pwrlvl) 27 { 28 psci_power_state_t state_info; 29 30 psci_acquire_pwr_domain_locks(end_pwrlvl, 31 cpu_idx); 32 33 /* 34 * Find out which retention states this CPU has exited from until the 35 * 'end_pwrlvl'. The exit retention state could be deeper than the entry 36 * state as a result of state coordination amongst other CPUs post wfi. 37 */ 38 psci_get_target_local_pwr_states(end_pwrlvl, &state_info); 39 40 /* 41 * Plat. management: Allow the platform to do operations 42 * on waking up from retention. 43 */ 44 psci_plat_pm_ops->pwr_domain_suspend_finish(&state_info); 45 46 /* 47 * Set the requested and target state of this CPU and all the higher 48 * power domain levels for this CPU to run. 49 */ 50 psci_set_pwr_domains_to_run(end_pwrlvl); 51 52 psci_release_pwr_domain_locks(end_pwrlvl, 53 cpu_idx); 54 } 55 56 /******************************************************************************* 57 * This function does generic and platform specific suspend to power down 58 * operations. 59 ******************************************************************************/ 60 static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, 61 entry_point_info_t *ep, 62 psci_power_state_t *state_info) 63 { 64 unsigned int max_off_lvl = psci_find_max_off_lvl(state_info); 65 66 /* Save PSCI target power level for the suspend finisher handler */ 67 psci_set_suspend_pwrlvl(end_pwrlvl); 68 69 /* 70 * Flush the target power level as it might be accessed on power up with 71 * Data cache disabled. 72 */ 73 psci_flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); 74 75 /* 76 * Call the cpu suspend handler registered by the Secure Payload 77 * Dispatcher to let it do any book-keeping. If the handler encounters an 78 * error, it's expected to assert within 79 */ 80 if (psci_spd_pm && psci_spd_pm->svc_suspend) 81 psci_spd_pm->svc_suspend(max_off_lvl); 82 83 /* 84 * Store the re-entry information for the non-secure world. 85 */ 86 cm_init_my_context(ep); 87 88 #if ENABLE_RUNTIME_INSTRUMENTATION 89 90 /* 91 * Flush cache line so that even if CPU power down happens 92 * the timestamp update is reflected in memory. 93 */ 94 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 95 RT_INSTR_ENTER_CFLUSH, 96 PMF_CACHE_MAINT); 97 #endif 98 99 /* 100 * Arch. management. Initiate power down sequence. 101 * TODO : Introduce a mechanism to query the cache level to flush 102 * and the cpu-ops power down to perform from the platform. 103 */ 104 psci_do_pwrdown_sequence(max_off_lvl); 105 106 #if ENABLE_RUNTIME_INSTRUMENTATION 107 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 108 RT_INSTR_EXIT_CFLUSH, 109 PMF_NO_CACHE_MAINT); 110 #endif 111 } 112 113 /******************************************************************************* 114 * Top level handler which is called when a cpu wants to suspend its execution. 115 * It is assumed that along with suspending the cpu power domain, power domains 116 * at higher levels until the target power level will be suspended as well. It 117 * coordinates with the platform to negotiate the target state for each of 118 * the power domain level till the target power domain level. It then performs 119 * generic, architectural, platform setup and state management required to 120 * suspend that power domain level and power domain levels below it. 121 * e.g. For a cpu that's to be suspended, it could mean programming the 122 * power controller whereas for a cluster that's to be suspended, it will call 123 * the platform specific code which will disable coherency at the interconnect 124 * level if the cpu is the last in the cluster and also the program the power 125 * controller. 126 * 127 * All the required parameter checks are performed at the beginning and after 128 * the state transition has been done, no further error is expected and it is 129 * not possible to undo any of the actions taken beyond that point. 130 ******************************************************************************/ 131 void psci_cpu_suspend_start(entry_point_info_t *ep, 132 unsigned int end_pwrlvl, 133 psci_power_state_t *state_info, 134 unsigned int is_power_down_state) 135 { 136 int skip_wfi = 0; 137 unsigned int idx = plat_my_core_pos(); 138 139 /* 140 * This function must only be called on platforms where the 141 * CPU_SUSPEND platform hooks have been implemented. 142 */ 143 assert(psci_plat_pm_ops->pwr_domain_suspend && 144 psci_plat_pm_ops->pwr_domain_suspend_finish); 145 146 /* 147 * This function acquires the lock corresponding to each power 148 * level so that by the time all locks are taken, the system topology 149 * is snapshot and state management can be done safely. 150 */ 151 psci_acquire_pwr_domain_locks(end_pwrlvl, 152 idx); 153 154 /* 155 * We check if there are any pending interrupts after the delay 156 * introduced by lock contention to increase the chances of early 157 * detection that a wake-up interrupt has fired. 158 */ 159 if (read_isr_el1()) { 160 skip_wfi = 1; 161 goto exit; 162 } 163 164 /* 165 * This function is passed the requested state info and 166 * it returns the negotiated state info for each power level upto 167 * the end level specified. 168 */ 169 psci_do_state_coordination(end_pwrlvl, state_info); 170 171 #if ENABLE_PSCI_STAT 172 /* Update the last cpu for each level till end_pwrlvl */ 173 psci_stats_update_pwr_down(end_pwrlvl, state_info); 174 #endif 175 176 if (is_power_down_state) 177 psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); 178 179 /* 180 * Plat. management: Allow the platform to perform the 181 * necessary actions to turn off this cpu e.g. set the 182 * platform defined mailbox with the psci entrypoint, 183 * program the power controller etc. 184 */ 185 psci_plat_pm_ops->pwr_domain_suspend(state_info); 186 187 #if ENABLE_PSCI_STAT 188 plat_psci_stat_accounting_start(state_info); 189 #endif 190 191 exit: 192 /* 193 * Release the locks corresponding to each power level in the 194 * reverse order to which they were acquired. 195 */ 196 psci_release_pwr_domain_locks(end_pwrlvl, 197 idx); 198 if (skip_wfi) 199 return; 200 201 if (is_power_down_state) { 202 #if ENABLE_RUNTIME_INSTRUMENTATION 203 204 /* 205 * Update the timestamp with cache off. We assume this 206 * timestamp can only be read from the current CPU and the 207 * timestamp cache line will be flushed before return to 208 * normal world on wakeup. 209 */ 210 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 211 RT_INSTR_ENTER_HW_LOW_PWR, 212 PMF_NO_CACHE_MAINT); 213 #endif 214 215 /* The function calls below must not return */ 216 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) 217 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(state_info); 218 else 219 psci_power_down_wfi(); 220 } 221 222 #if ENABLE_RUNTIME_INSTRUMENTATION 223 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 224 RT_INSTR_ENTER_HW_LOW_PWR, 225 PMF_NO_CACHE_MAINT); 226 #endif 227 228 #if ENABLE_PSCI_STAT 229 plat_psci_stat_accounting_start(state_info); 230 #endif 231 232 /* 233 * We will reach here if only retention/standby states have been 234 * requested at multiple power levels. This means that the cpu 235 * context will be preserved. 236 */ 237 wfi(); 238 239 #if ENABLE_PSCI_STAT 240 plat_psci_stat_accounting_stop(state_info); 241 psci_stats_update_pwr_up(end_pwrlvl, state_info); 242 #endif 243 244 #if ENABLE_RUNTIME_INSTRUMENTATION 245 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 246 RT_INSTR_EXIT_HW_LOW_PWR, 247 PMF_NO_CACHE_MAINT); 248 #endif 249 250 /* 251 * After we wake up from context retaining suspend, call the 252 * context retaining suspend finisher. 253 */ 254 psci_suspend_to_standby_finisher(idx, end_pwrlvl); 255 } 256 257 /******************************************************************************* 258 * The following functions finish an earlier suspend request. They 259 * are called by the common finisher routine in psci_common.c. The `state_info` 260 * is the psci_power_state from which this CPU has woken up from. 261 ******************************************************************************/ 262 void psci_cpu_suspend_finish(unsigned int cpu_idx, 263 psci_power_state_t *state_info) 264 { 265 unsigned int counter_freq; 266 unsigned int max_off_lvl; 267 268 /* Ensure we have been woken up from a suspended state */ 269 assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ 270 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); 271 272 /* 273 * Plat. management: Perform the platform specific actions 274 * before we change the state of the cpu e.g. enabling the 275 * gic or zeroing the mailbox register. If anything goes 276 * wrong then assert as there is no way to recover from this 277 * situation. 278 */ 279 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 280 281 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 282 /* Arch. management: Enable the data cache, stack memory maintenance. */ 283 psci_do_pwrup_cache_maintenance(); 284 #endif 285 286 /* Re-init the cntfrq_el0 register */ 287 counter_freq = plat_get_syscnt_freq2(); 288 write_cntfrq_el0(counter_freq); 289 290 /* 291 * Call the cpu suspend finish handler registered by the Secure Payload 292 * Dispatcher to let it do any bookeeping. If the handler encounters an 293 * error, it's expected to assert within 294 */ 295 if (psci_spd_pm && psci_spd_pm->svc_suspend) { 296 max_off_lvl = psci_find_max_off_lvl(state_info); 297 assert (max_off_lvl != PSCI_INVALID_PWR_LVL); 298 psci_spd_pm->svc_suspend_finish(max_off_lvl); 299 } 300 301 /* Invalidate the suspend level for the cpu */ 302 psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); 303 304 /* 305 * Generic management: Now we just need to retrieve the 306 * information that we had stashed away during the suspend 307 * call to set this cpu on its way. 308 */ 309 cm_prepare_el3_exit(NON_SECURE); 310 } 311