Merge "xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled()" into integration

xlat lib v2: Add support to pass shareability attribute for normal memory region

Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. i

xlat lib v2: Add support to pass shareability attribute for normal memory region

Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. it defaults to inner shareability.

There are platforms where memories (like SRAM) are not placed at snoopable
region in advaned interconnect like CCN/CMN hence snoopable transaction is
not possible to these memory. Though These memories could be mapped in MMU
as MT_NON_CACHEABLE, data caches benefits won't be available.

If these memories are mapped as cacheable with non-shareable attribute,
when only one core is running like at boot time, MMU data cached could be
used for faster execution. Hence adding support to pass the shareability
attribute for memory regions.

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754

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xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled()

Using get_current_el_maybe_constant() produces more optimized code
because in most cases, we know the exception level at bu

xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled()

Using get_current_el_maybe_constant() produces more optimized code
because in most cases, we know the exception level at build-time.
For example, BL31 runs at EL3, so unneeded code will be trimmed.

[before]

0000000000000000 <is_dcache_enabled>:
0: d5384240 mrs x0, currentel
4: 53020c00 ubfx w0, w0, #2, #2
8: 7100041f cmp w0, #0x1
c: 54000081 b.ne 1c <is_dcache_enabled+0x1c> // b.any
10: d5381000 mrs x0, sctlr_el1
14: 53020800 ubfx w0, w0, #2, #1
18: d65f03c0 ret
1c: 7100081f cmp w0, #0x2
20: 54000061 b.ne 2c <is_dcache_enabled+0x2c> // b.any
24: d53c1000 mrs x0, sctlr_el2
28: 17fffffb b 14 <is_dcache_enabled+0x14>
2c: d53e1000 mrs x0, sctlr_el3
30: 17fffff9 b 14 <is_dcache_enabled+0x14>

[after]

0000000000000000 <is_dcache_enabled>:
0: d53e1000 mrs x0, sctlr_el3
4: 53020800 ubfx w0, w0, #2, #1
8: d65f03c0 ret

Change-Id: I3698fae9b517022ff9fbfd4cad3a320c6e137e10
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES

If PLAT_RO_XLAT_TABLES is defined, the base xlat table goes to the
.rodata section instead of .bss section.

This causes a warning like:

xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES

If PLAT_RO_XLAT_TABLES is defined, the base xlat table goes to the
.rodata section instead of .bss section.

This causes a warning like:

/tmp/ccswitLr.s: Assembler messages:
/tmp/ccswitLr.s:297: Warning: setting incorrect section attributes for .rodata

It is practically no problem, but I want to keep the build log clean.

Put the base table into the "base_xlat_table" section to suppress the
assembler warnings.

The linker script determines its final destination; rodata section if
PLAT_RO_XLAT_TABLES=1, or bss section otherwise. So, the result is the
same.

Change-Id: Ic85d1d2dddd9b5339289fc2378cbcb21dd7db02e
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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xlat_tables_v2: add enable_mmu()

enable_mmu_* has a different function name, so it is not handy in the
shared code. enable_mmu() calls an appropriate one depending on the
exception level.

Change-Id

xlat_tables_v2: add enable_mmu()

enable_mmu_* has a different function name, so it is not handy in the
shared code. enable_mmu() calls an appropriate one depending on the
exception level.

Change-Id: I0657968bfcb91c32733f75f9259f550a5c35b1c3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}

xlat_tables_v2_helpers.h defines two quite similar macros,
REGISTER_XLAT_CONTEXT_FULL_SPEC and REGISTER_XLAT_CONTEXT_RO_BASE_TAB

xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}

xlat_tables_v2_helpers.h defines two quite similar macros,
REGISTER_XLAT_CONTEXT_FULL_SPEC and REGISTER_XLAT_CONTEXT_RO_BASE_TABLE.

Only the difference is the section of _ctx_name##_base_xlat_table.

Parameterize it and unify these two macros.

The base xlat table goes into the .bss section by default.
If PLAT_RO_XLAT_TABLES is defined, it goes into the .rodata section.

Change-Id: I8b02f4da98f0c272e348a200cebd89f479099c55
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Read-only xlat tables for BL31 memory

This patch introduces a build flag which allows the xlat tables
to be mapped in a read-only region within BL31 memory. It makes it
much harder for someone who h

Read-only xlat tables for BL31 memory

This patch introduces a build flag which allows the xlat tables
to be mapped in a read-only region within BL31 memory. It makes it
much harder for someone who has acquired the ability to write to
arbitrary secure memory addresses to gain control of the
translation tables.

The memory attributes of the descriptors describing the tables
themselves are changed to read-only secure data. This change
happens at the end of BL31 runtime setup. Until this point, the
tables have read-write permissions. This gives a window of
opportunity for changes to be made to the tables with the MMU on
(e.g. reclaiming init code). No changes can be made to the tables
with the MMU turned on from this point onwards. This change is also
enabled for sp_min and tspd.

To make all this possible, the base table was moved to .rodata. The
penalty we pay is that now .rodata must be aligned to the size of
the base table (512B alignment). Still, this is better than putting
the base table with the higher level tables in the xlat_table
section, as that would cost us a full 4KB page.

Changing the tables from read-write to read-only cannot be done with
the MMU on, as the break-before-make sequence would invalidate the
descriptor which resolves the level 3 page table where that very
descriptor is located. This would make the translation required for
writing the changes impossible, generating an MMU fault.

The caches are also flushed.

Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ibe5de307e6dc94c67d6186139ac3973516430466

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xlat_tables_v2: simplify end address checks in mmap_add_region_check()

Use end_va and end_pa defined at the beginning of this function.

Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c
Signed-o

xlat_tables_v2: simplify end address checks in mmap_add_region_check()

Use end_va and end_pa defined at the beginning of this function.

Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Coding guideline suggest not to use unsigned long

`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_regis

Coding guideline suggest not to use unsigned long

`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_register_t` - If it is supposed to be 32-bit
wide in AArch32 and 64-bit wide in AArch64.

Translation descriptors are always 32-bit wide, here
`uint32_t` is used to describe the `exact size` of
translation descriptors instead of `unsigned int` which
guarantees minimum 32-bits

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I6a2af2e8b3c71170e2634044e0b887f07a41677e

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xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config

The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did n

xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config

The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did not do the required
cache maintenance after the mmap tables are modified if
WARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned
off during power down, the tables in memory are accessed as part of cache
maintenance for power down, and the tables are not correct at this point which
results in a data abort.
This patch removes the optimization within xlat_change_mem_attributes_ctx()
when WARMBOOT_ENABLE_DCACHE_EARLY is enabled.

Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87

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Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the cod

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by add

Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.

Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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SPM: Move shim layer to TTBR1_EL1

This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also

SPM: Move shim layer to TTBR1_EL1

This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also, it always had to be mapped, forcing SPM to
generate translation tables that included the exception vectors as well
as the Partition memory regions. With this change, partitions can reduce
their address space size easily.

Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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xlat_tables_v2: Revert recent changes to remove recursion

This commit reverts the following commits:

- c54c7fc35842 ("xlat_tables_v2: print xlat tables without recursion")
- db8cac2d986a ("xlat_tab

xlat_tables_v2: Revert recent changes to remove recursion

This commit reverts the following commits:

- c54c7fc35842 ("xlat_tables_v2: print xlat tables without recursion")
- db8cac2d986a ("xlat_tables_v2: unmap region without recursion.")
- 0ffe269215bd ("xlat_tables_v2: map region without recursion.")

This was part of PR#1843.

A problem has been detected in one of our test run configurations
involving dynamic mapping of regions and it is blocking the next
release. Until the problem can be solved, it is safer to revert
the changes.

Change-Id: I3d5456e4dbebf291c8b74939c6fb02a912e0903b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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xlat_tables_v2: print xlat tables without recursion

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversa

xlat_tables_v2: print xlat tables without recursion

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.

fixes arm-software/tf-issues#664

Signed-off-by: David Pu <dpu@nvidia.com>

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xlat_tables_v2: unmap region without recursion.

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
or

xlat_tables_v2: unmap region without recursion.

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.

fixes arm-software/tf-issues#664

Signed-off-by: David Pu <dpu@nvidia.com>

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xlat_tables_v2: map region without recursion.

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
orde

xlat_tables_v2: map region without recursion.

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.

fixes arm-software/tf-issues#664

Signed-off-by: David Pu <dpu@nvidia.com>

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xlat_tables_v2: find VA/idx with helper functions.

This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by

xlat_tables_v2: find VA/idx with helper functions.

This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by the
specified mmap region. it reduces code duplication and cyclomatic code
complexity in xlat_tables_map/unmap_region functions.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>

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xlat_tables_v2: get unmap action type with helper function.

This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmappin

xlat_tables_v2: get unmap action type with helper function.

This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmapping the
specified region.
it reduces cyclomatic code complexity in xlat_tables_unmap_region function.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>

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xlat_tables_v2: mark 'xlat_clean_dcache_range' unused

The armclang compiler can warn if a variable is declared but
is never referenced. The '__attribute__((unused))' attribute
informs the compiler t

xlat_tables_v2: mark 'xlat_clean_dcache_range' unused

The armclang compiler can warn if a variable is declared but
is never referenced. The '__attribute__((unused))' attribute
informs the compiler to expect an unused variable, and tells
it not to issue a warning.

This patch marks the 'xlat_clean_dcache_range' function as
"unused" to fix this armclang compiler warning.

Change-Id: I7623f61c2975a01db4d1b80554dd4f9a9e0f7eb6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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