1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 17 /********************************************************************** 18 * Macros which create inline functions to read or write CPU system 19 * registers 20 *********************************************************************/ 21 22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 23 static inline u_register_t read_ ## _name(void) \ 24 { \ 25 u_register_t v; \ 26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 27 return v; \ 28 } 29 30 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 31 static inline void write_ ## _name(u_register_t v) \ 32 { \ 33 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 34 } 35 36 #define SYSREG_WRITE_CONST(reg_name, v) \ 37 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 38 39 /* Define read function for system register */ 40 #define DEFINE_SYSREG_READ_FUNC(_name) \ 41 _DEFINE_SYSREG_READ_FUNC(_name, _name) 42 43 /* Define read & write function for system register */ 44 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 45 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 46 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 47 48 /* Define read & write function for renamed system register */ 49 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 50 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 51 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 52 53 /* Define read function for renamed system register */ 54 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 55 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 56 57 /* Define write function for renamed system register */ 58 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 60 61 /********************************************************************** 62 * Macros to create inline functions for system instructions 63 *********************************************************************/ 64 65 /* Define function for simple system instruction */ 66 #define DEFINE_SYSOP_FUNC(_op) \ 67 static inline void _op(void) \ 68 { \ 69 __asm__ (#_op); \ 70 } 71 72 /* Define function for system instruction with type specifier */ 73 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 74 static inline void _op ## _type(void) \ 75 { \ 76 __asm__ (#_op " " #_type); \ 77 } 78 79 /* Define function for system instruction with register parameter */ 80 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 81 static inline void _op ## _type(uint64_t v) \ 82 { \ 83 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 84 } 85 86 /******************************************************************************* 87 * TLB maintenance accessor prototypes 88 ******************************************************************************/ 89 90 #if ERRATA_A57_813419 91 /* 92 * Define function for TLBI instruction with type specifier that implements 93 * the workaround for errata 813419 of Cortex-A57. 94 */ 95 #define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\ 96 static inline void tlbi ## _type(void) \ 97 { \ 98 __asm__("tlbi " #_type "\n" \ 99 "dsb ish\n" \ 100 "tlbi " #_type); \ 101 } 102 103 /* 104 * Define function for TLBI instruction with register parameter that implements 105 * the workaround for errata 813419 of Cortex-A57. 106 */ 107 #define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \ 108 static inline void tlbi ## _type(uint64_t v) \ 109 { \ 110 __asm__("tlbi " #_type ", %0\n" \ 111 "dsb ish\n" \ 112 "tlbi " #_type ", %0" : : "r" (v)); \ 113 } 114 #endif /* ERRATA_A57_813419 */ 115 116 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 117 /* 118 * Define function for DC instruction with register parameter that enables 119 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. 120 */ 121 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ 122 static inline void dc ## _name(uint64_t v) \ 123 { \ 124 __asm__("dc " #_type ", %0" : : "r" (v)); \ 125 } 126 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ 127 128 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 129 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 130 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 131 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 132 #if ERRATA_A57_813419 133 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3) 134 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is) 135 #else 136 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 137 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 138 #endif 139 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 140 141 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 142 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 143 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 144 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 145 #if ERRATA_A57_813419 146 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is) 147 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is) 148 #else 149 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 150 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 151 #endif 152 153 /******************************************************************************* 154 * Cache maintenance accessor prototypes 155 ******************************************************************************/ 156 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 157 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 158 #if ERRATA_A53_827319 159 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) 160 #else 161 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 162 #endif 163 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 164 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) 165 #else 166 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 167 #endif 168 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 169 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 170 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 171 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) 172 #else 173 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 174 #endif 175 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 176 177 /******************************************************************************* 178 * Address translation accessor prototypes 179 ******************************************************************************/ 180 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 181 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 182 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 183 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 184 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 185 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 186 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 187 188 void flush_dcache_range(uintptr_t addr, size_t size); 189 void clean_dcache_range(uintptr_t addr, size_t size); 190 void inv_dcache_range(uintptr_t addr, size_t size); 191 192 void dcsw_op_louis(u_register_t op_type); 193 void dcsw_op_all(u_register_t op_type); 194 195 void disable_mmu_el1(void); 196 void disable_mmu_el3(void); 197 void disable_mmu_icache_el1(void); 198 void disable_mmu_icache_el3(void); 199 200 /******************************************************************************* 201 * Misc. accessor prototypes 202 ******************************************************************************/ 203 204 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 205 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 206 207 DEFINE_SYSREG_RW_FUNCS(par_el1) 208 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) 209 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) 210 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) 211 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) 212 DEFINE_SYSREG_READ_FUNC(id_afr0_el1) 213 DEFINE_SYSREG_READ_FUNC(CurrentEl) 214 DEFINE_SYSREG_READ_FUNC(ctr_el0) 215 DEFINE_SYSREG_RW_FUNCS(daif) 216 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 217 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 218 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 219 DEFINE_SYSREG_RW_FUNCS(elr_el1) 220 DEFINE_SYSREG_RW_FUNCS(elr_el2) 221 DEFINE_SYSREG_RW_FUNCS(elr_el3) 222 223 DEFINE_SYSOP_FUNC(wfi) 224 DEFINE_SYSOP_FUNC(wfe) 225 DEFINE_SYSOP_FUNC(sev) 226 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 227 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 228 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 229 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 230 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 231 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 232 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 233 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 234 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 235 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 236 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 237 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 238 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 239 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 240 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 241 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 242 DEFINE_SYSOP_FUNC(isb) 243 244 static inline void enable_irq(void) 245 { 246 /* 247 * The compiler memory barrier will prevent the compiler from 248 * scheduling non-volatile memory access after the write to the 249 * register. 250 * 251 * This could happen if some initialization code issues non-volatile 252 * accesses to an area used by an interrupt handler, in the assumption 253 * that it is safe as the interrupts are disabled at the time it does 254 * that (according to program order). However, non-volatile accesses 255 * are not necessarily in program order relatively with volatile inline 256 * assembly statements (and volatile accesses). 257 */ 258 COMPILER_BARRIER(); 259 write_daifclr(DAIF_IRQ_BIT); 260 isb(); 261 } 262 263 static inline void enable_fiq(void) 264 { 265 COMPILER_BARRIER(); 266 write_daifclr(DAIF_FIQ_BIT); 267 isb(); 268 } 269 270 static inline void enable_serror(void) 271 { 272 COMPILER_BARRIER(); 273 write_daifclr(DAIF_ABT_BIT); 274 isb(); 275 } 276 277 static inline void enable_debug_exceptions(void) 278 { 279 COMPILER_BARRIER(); 280 write_daifclr(DAIF_DBG_BIT); 281 isb(); 282 } 283 284 static inline void disable_irq(void) 285 { 286 COMPILER_BARRIER(); 287 write_daifset(DAIF_IRQ_BIT); 288 isb(); 289 } 290 291 static inline void disable_fiq(void) 292 { 293 COMPILER_BARRIER(); 294 write_daifset(DAIF_FIQ_BIT); 295 isb(); 296 } 297 298 static inline void disable_serror(void) 299 { 300 COMPILER_BARRIER(); 301 write_daifset(DAIF_ABT_BIT); 302 isb(); 303 } 304 305 static inline void disable_debug_exceptions(void) 306 { 307 COMPILER_BARRIER(); 308 write_daifset(DAIF_DBG_BIT); 309 isb(); 310 } 311 312 #if !ERROR_DEPRECATED 313 uint32_t get_afflvl_shift(uint32_t); 314 uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t); 315 316 void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 317 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 318 #endif 319 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 320 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 321 322 /******************************************************************************* 323 * System register accessor prototypes 324 ******************************************************************************/ 325 DEFINE_SYSREG_READ_FUNC(midr_el1) 326 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 327 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) 328 329 DEFINE_SYSREG_RW_FUNCS(scr_el3) 330 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 331 332 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 333 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 334 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 335 336 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 337 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 338 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 339 340 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 341 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 342 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 343 344 DEFINE_SYSREG_RW_FUNCS(esr_el1) 345 DEFINE_SYSREG_RW_FUNCS(esr_el2) 346 DEFINE_SYSREG_RW_FUNCS(esr_el3) 347 348 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 349 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 350 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 351 352 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 353 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 354 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 355 356 DEFINE_SYSREG_RW_FUNCS(far_el1) 357 DEFINE_SYSREG_RW_FUNCS(far_el2) 358 DEFINE_SYSREG_RW_FUNCS(far_el3) 359 360 DEFINE_SYSREG_RW_FUNCS(mair_el1) 361 DEFINE_SYSREG_RW_FUNCS(mair_el2) 362 DEFINE_SYSREG_RW_FUNCS(mair_el3) 363 364 DEFINE_SYSREG_RW_FUNCS(amair_el1) 365 DEFINE_SYSREG_RW_FUNCS(amair_el2) 366 DEFINE_SYSREG_RW_FUNCS(amair_el3) 367 368 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 369 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 370 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 371 372 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 373 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 374 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 375 376 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 377 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 378 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 379 380 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 381 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 382 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 383 384 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 385 386 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 387 388 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 389 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 390 391 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 392 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 393 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 394 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 395 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 396 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 397 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 398 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 399 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 400 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 401 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 402 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 403 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 404 405 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 406 CNTP_CTL_ENABLE_MASK) 407 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 408 CNTP_CTL_IMASK_MASK) 409 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 410 CNTP_CTL_ISTATUS_MASK) 411 412 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 413 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 414 415 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 416 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 417 418 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 419 420 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 421 422 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 423 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 424 425 DEFINE_SYSREG_READ_FUNC(isr_el1) 426 427 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 428 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 429 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 430 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 431 432 /* GICv3 System Registers */ 433 434 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 435 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 436 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 437 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 438 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 439 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 440 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 441 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 442 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 443 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 444 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 445 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 446 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 447 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 448 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 449 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 450 451 DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) 452 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 453 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 454 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 455 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 456 457 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 458 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 459 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 460 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 461 462 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 463 464 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 465 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 466 467 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 468 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 469 470 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 471 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 472 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 473 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 474 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 475 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 476 477 /* Armv8.2 Registers */ 478 DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) 479 480 /* Armv8.3 Pointer Authentication Registers */ 481 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) 482 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) 483 484 #define IS_IN_EL(x) \ 485 (GET_EL(read_CurrentEl()) == MODE_EL##x) 486 487 #define IS_IN_EL1() IS_IN_EL(1) 488 #define IS_IN_EL2() IS_IN_EL(2) 489 #define IS_IN_EL3() IS_IN_EL(3) 490 491 static inline unsigned int get_current_el(void) 492 { 493 return GET_EL(read_CurrentEl()); 494 } 495 496 /* 497 * Check if an EL is implemented from AA64PFR0 register fields. 498 */ 499 static inline uint64_t el_implemented(unsigned int el) 500 { 501 if (el > 3U) { 502 return EL_IMPL_NONE; 503 } else { 504 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 505 506 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 507 } 508 } 509 510 #if !ERROR_DEPRECATED 511 #define EL_IMPLEMENTED(_el) el_implemented(_el) 512 #endif 513 514 /* Previously defined accesor functions with incomplete register names */ 515 516 #define read_current_el() read_CurrentEl() 517 518 #define dsb() dsbsy() 519 520 #define read_midr() read_midr_el1() 521 522 #define read_mpidr() read_mpidr_el1() 523 524 #define read_scr() read_scr_el3() 525 #define write_scr(_v) write_scr_el3(_v) 526 527 #define read_hcr() read_hcr_el2() 528 #define write_hcr(_v) write_hcr_el2(_v) 529 530 #define read_cpacr() read_cpacr_el1() 531 #define write_cpacr(_v) write_cpacr_el1(_v) 532 533 #endif /* ARCH_HELPERS_H */ 534