1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 22 #include <arm_def.h> 23 #include <board_css_def.h> 24 #include <common_def.h> 25 #include <css_def.h> 26 #if TRUSTED_BOARD_BOOT 27 #include <mbedtls_config.h> 28 #endif 29 #include <soc_css_def.h> 30 #include <tzc400.h> 31 #include <v2m_def.h> 32 #include "../juno_def.h" 33 34 /* Required platform porting definitions */ 35 /* Juno supports system power domain */ 36 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 37 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 38 JUNO_CLUSTER_COUNT + \ 39 PLATFORM_CORE_COUNT) 40 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 41 JUNO_CLUSTER1_CORE_COUNT) 42 43 /* Cryptocell HW Base address */ 44 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 45 46 /* 47 * Other platform porting definitions are provided by included headers 48 */ 49 50 /* 51 * Required ARM standard platform porting definitions 52 */ 53 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 54 55 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 56 57 /* Use the bypass address */ 58 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 59 BL1_ROM_BYPASS_OFFSET) 60 61 #define NSRAM_BASE UL(0x2e000000) 62 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 63 64 /* virtual address used by dynamic mem_protect for chunk_base */ 65 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 66 67 /* 68 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 69 */ 70 71 #if USE_ROMLIB 72 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 73 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 74 #else 75 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 76 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 77 #endif 78 79 /* 80 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 81 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 82 * flash 83 */ 84 85 #if TRUSTED_BOARD_BOOT 86 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 87 #else 88 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 89 #endif /* TRUSTED_BOARD_BOOT */ 90 91 /* 92 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 93 * plat_arm_mmap array defined for each BL stage. 94 */ 95 #ifdef IMAGE_BL1 96 # define PLAT_ARM_MMAP_ENTRIES 7 97 # define MAX_XLAT_TABLES 4 98 #endif 99 100 #ifdef IMAGE_BL2 101 #ifdef SPD_opteed 102 # define PLAT_ARM_MMAP_ENTRIES 11 103 # define MAX_XLAT_TABLES 5 104 #else 105 # define PLAT_ARM_MMAP_ENTRIES 10 106 # define MAX_XLAT_TABLES 4 107 #endif 108 #endif 109 110 #ifdef IMAGE_BL2U 111 # define PLAT_ARM_MMAP_ENTRIES 5 112 # define MAX_XLAT_TABLES 3 113 #endif 114 115 #ifdef IMAGE_BL31 116 # define PLAT_ARM_MMAP_ENTRIES 7 117 # define MAX_XLAT_TABLES 3 118 #endif 119 120 #ifdef IMAGE_BL32 121 # define PLAT_ARM_MMAP_ENTRIES 6 122 # define MAX_XLAT_TABLES 4 123 #endif 124 125 /* 126 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 127 * plus a little space for growth. 128 */ 129 #if TRUSTED_BOARD_BOOT 130 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 131 #else 132 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 133 #endif 134 135 /* 136 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 137 * little space for growth. 138 */ 139 #if TRUSTED_BOARD_BOOT 140 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 141 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000) 142 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 143 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 144 #else 145 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1C000) 146 #endif 147 #else 148 # define PLAT_ARM_MAX_BL2_SIZE UL(0xF000) 149 #endif 150 151 /* 152 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 153 * calculated using the current BL31 PROGBITS debug size plus the sizes of 154 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 155 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 156 */ 157 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000) 158 159 #if JUNO_AARCH32_EL3_RUNTIME 160 /* 161 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 162 * calculated using the current BL32 PROGBITS debug size plus the sizes of 163 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 164 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 165 */ 166 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000) 167 #endif 168 169 /* 170 * Size of cacheable stacks 171 */ 172 #if defined(IMAGE_BL1) 173 # if TRUSTED_BOARD_BOOT 174 # define PLATFORM_STACK_SIZE UL(0x1000) 175 # else 176 # define PLATFORM_STACK_SIZE UL(0x440) 177 # endif 178 #elif defined(IMAGE_BL2) 179 # if TRUSTED_BOARD_BOOT 180 # define PLATFORM_STACK_SIZE UL(0x1000) 181 # else 182 # define PLATFORM_STACK_SIZE UL(0x400) 183 # endif 184 #elif defined(IMAGE_BL2U) 185 # define PLATFORM_STACK_SIZE UL(0x400) 186 #elif defined(IMAGE_BL31) 187 # if PLAT_XLAT_TABLES_DYNAMIC 188 # define PLATFORM_STACK_SIZE UL(0x800) 189 # else 190 # define PLATFORM_STACK_SIZE UL(0x400) 191 # endif 192 #elif defined(IMAGE_BL32) 193 # define PLATFORM_STACK_SIZE UL(0x440) 194 #endif 195 196 /* 197 * Since free SRAM space is scant, enable the ASSERTION message size 198 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 199 */ 200 #define PLAT_LOG_LEVEL_ASSERT 40 201 202 /* CCI related constants */ 203 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 204 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 205 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 206 207 /* System timer related constants */ 208 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 209 210 /* TZC related constants */ 211 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 212 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 213 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 214 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 215 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 217 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 218 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 219 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 220 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 221 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 223 224 /* 225 * Required ARM CSS based platform porting definitions 226 */ 227 228 /* GIC related constants (no GICR in GIC-400) */ 229 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 230 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 231 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 232 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 233 234 /* MHU related constants */ 235 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 236 237 /* 238 * Base address of the first memory region used for communication between AP 239 * and SCP. Used by the BOM and SCPI protocols. 240 */ 241 #if !CSS_USE_SCMI_SDS_DRIVER 242 /* 243 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 244 * means the SCP/AP configuration data gets overwritten when the AP initiates 245 * communication with the SCP. The configuration data is expected to be a 246 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 247 * which CPU is the primary, according to the shift and mask definitions below. 248 */ 249 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 250 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 251 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 252 #endif 253 254 /* 255 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 256 * SCP_BL2 size plus a little space for growth. 257 */ 258 #define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000) 259 260 /* 261 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 262 * SCP_BL2U size plus a little space for growth. 263 */ 264 #define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000) 265 266 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 267 CSS_G1S_IRQ_PROPS(grp), \ 268 ARM_G1S_IRQ_PROPS(grp), \ 269 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 270 (grp), GIC_INTR_CFG_LEVEL), \ 271 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 272 (grp), GIC_INTR_CFG_LEVEL), \ 273 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 274 (grp), GIC_INTR_CFG_LEVEL), \ 275 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 276 (grp), GIC_INTR_CFG_LEVEL), \ 277 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 278 (grp), GIC_INTR_CFG_LEVEL), \ 279 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 280 (grp), GIC_INTR_CFG_LEVEL), \ 281 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 282 (grp), GIC_INTR_CFG_LEVEL), \ 283 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 284 (grp), GIC_INTR_CFG_LEVEL) 285 286 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 287 288 /* 289 * Required ARM CSS SoC based platform porting definitions 290 */ 291 292 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 293 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 294 295 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 296 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 297 298 /* System power domain level */ 299 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 300 301 #endif /* PLATFORM_DEF_H */ 302