1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <cci.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <errno.h> 14 #include <generic_delay_timer.h> 15 #include <gicv2.h> 16 #include <hi3660.h> 17 #include <mmio.h> 18 #include <hisi_ipc.h> 19 #include <interrupt_mgmt.h> 20 #include <interrupt_props.h> 21 #include <pl011.h> 22 #include <platform.h> 23 #include <platform_def.h> 24 25 #include "hikey960_def.h" 26 #include "hikey960_private.h" 27 28 /* 29 * The next 2 constants identify the extents of the code & RO data region. 30 * These addresses are used by the MMU setup code and therefore they must be 31 * page-aligned. It is the responsibility of the linker script to ensure that 32 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 33 */ 34 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 35 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 36 37 /* 38 * The next 2 constants identify the extents of the coherent memory region. 39 * These addresses are used by the MMU setup code and therefore they must be 40 * page-aligned. It is the responsibility of the linker script to ensure that 41 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 42 * page-aligned addresses. 43 */ 44 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 45 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 46 47 static entry_point_info_t bl32_ep_info; 48 static entry_point_info_t bl33_ep_info; 49 static console_pl011_t console; 50 51 /****************************************************************************** 52 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 53 * interrupts. 54 *****************************************************************************/ 55 static const interrupt_prop_t g0_interrupt_props[] = { 56 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 57 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 58 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 59 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 60 }; 61 62 const gicv2_driver_data_t hikey960_gic_data = { 63 .gicd_base = GICD_REG_BASE, 64 .gicc_base = GICC_REG_BASE, 65 .interrupt_props = g0_interrupt_props, 66 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 67 }; 68 69 static const int cci_map[] = { 70 CCI400_SL_IFACE3_CLUSTER_IX, 71 CCI400_SL_IFACE4_CLUSTER_IX 72 }; 73 74 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 75 { 76 entry_point_info_t *next_image_info; 77 78 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 79 80 /* None of the images on this platform can have 0x0 as the entrypoint */ 81 if (next_image_info->pc) 82 return next_image_info; 83 return NULL; 84 } 85 86 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 87 u_register_t arg2, u_register_t arg3) 88 { 89 unsigned int id, uart_base; 90 void *from_bl2; 91 92 from_bl2 = (void *) arg0; 93 94 generic_delay_timer_init(); 95 hikey960_read_boardid(&id); 96 if (id == 5300) 97 uart_base = PL011_UART5_BASE; 98 else 99 uart_base = PL011_UART6_BASE; 100 101 /* Initialize the console to provide early debug support */ 102 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 103 PL011_BAUDRATE, &console); 104 105 /* Initialize CCI driver */ 106 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map)); 107 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 108 109 /* 110 * Check params passed from BL2 should not be NULL, 111 */ 112 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 113 assert(params_from_bl2 != NULL); 114 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 115 assert(params_from_bl2->h.version >= VERSION_2); 116 117 bl_params_node_t *bl_params = params_from_bl2->head; 118 119 /* 120 * Copy BL33 and BL32 (if present), entry point information. 121 * They are stored in Secure RAM, in BL2's address space. 122 */ 123 while (bl_params) { 124 if (bl_params->image_id == BL32_IMAGE_ID) 125 bl32_ep_info = *bl_params->ep_info; 126 127 if (bl_params->image_id == BL33_IMAGE_ID) 128 bl33_ep_info = *bl_params->ep_info; 129 130 bl_params = bl_params->next_params_info; 131 } 132 133 if (bl33_ep_info.pc == 0) 134 panic(); 135 } 136 137 void bl31_plat_arch_setup(void) 138 { 139 hikey960_init_mmu_el3(BL31_BASE, 140 BL31_LIMIT - BL31_BASE, 141 BL31_RO_BASE, 142 BL31_RO_LIMIT, 143 BL31_COHERENT_RAM_BASE, 144 BL31_COHERENT_RAM_LIMIT); 145 } 146 147 static void hikey960_edma_init(void) 148 { 149 int i; 150 uint32_t non_secure; 151 152 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 153 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 154 155 for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) { 156 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 157 } 158 } 159 160 void bl31_platform_setup(void) 161 { 162 /* Initialize the GIC driver, cpu and distributor interfaces */ 163 gicv2_driver_init(&hikey960_gic_data); 164 gicv2_distif_init(); 165 gicv2_pcpu_distif_init(); 166 gicv2_cpuif_enable(); 167 168 hikey960_edma_init(); 169 170 hisi_ipc_init(); 171 } 172 173 #ifdef SPD_none 174 static uint64_t hikey_debug_fiq_handler(uint32_t id, 175 uint32_t flags, 176 void *handle, 177 void *cookie) 178 { 179 int intr, intr_raw; 180 181 /* Acknowledge interrupt */ 182 intr_raw = plat_ic_acknowledge_interrupt(); 183 intr = plat_ic_get_interrupt_id(intr_raw); 184 ERROR("Invalid interrupt: intr=%d\n", intr); 185 console_flush(); 186 panic(); 187 188 return 0; 189 } 190 #endif 191 192 void bl31_plat_runtime_setup(void) 193 { 194 #ifdef SPD_none 195 uint32_t flags; 196 int32_t rc; 197 198 flags = 0; 199 set_interrupt_rm_flag(flags, NON_SECURE); 200 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 201 hikey_debug_fiq_handler, 202 flags); 203 if (rc != 0) 204 panic(); 205 #endif 206 } 207