1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <debug.h> 10 #include <gpc.h> 11 #include <stdbool.h> 12 #include <plat_imx8.h> 13 #include <psci.h> 14 #include <mmio.h> 15 16 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 17 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 18 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 19 20 int imx_pwr_domain_on(u_register_t mpidr) 21 { 22 unsigned int core_id; 23 uint64_t base_addr = BL31_BASE; 24 25 core_id = MPIDR_AFFLVL0_VAL(mpidr); 26 27 /* set the secure entrypoint */ 28 imx_set_cpu_secure_entry(core_id, base_addr); 29 /* power up the core */ 30 imx_set_cpu_pwr_on(core_id); 31 32 return PSCI_E_SUCCESS; 33 } 34 35 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 36 { 37 /* program the GIC per cpu dist and rdist interface */ 38 plat_gic_pcpu_init(); 39 /* enable the GICv3 cpu interface */ 40 plat_gic_cpuif_enable(); 41 } 42 43 void imx_pwr_domain_off(const psci_power_state_t *target_state) 44 { 45 uint64_t mpidr = read_mpidr_el1(); 46 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 47 48 /* disable the GIC cpu interface first */ 49 plat_gic_cpuif_disable(); 50 /* config the core for power down */ 51 imx_set_cpu_pwr_off(core_id); 52 } 53 54 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 55 { 56 /* The non-secure entrypoint should be in RAM space */ 57 if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET) 58 return PSCI_E_INVALID_PARAMS; 59 60 return PSCI_E_SUCCESS; 61 } 62 63 int imx_validate_power_state(unsigned int power_state, 64 psci_power_state_t *req_state) 65 { 66 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 67 int pwr_type = psci_get_pstate_type(power_state); 68 int state_id = psci_get_pstate_id(power_state); 69 70 if (pwr_lvl > PLAT_MAX_PWR_LVL) 71 return PSCI_E_INVALID_PARAMS; 72 73 if (pwr_type == PSTATE_TYPE_STANDBY) { 74 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 75 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 76 } 77 78 if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) { 79 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; 80 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; 81 } 82 83 return PSCI_E_SUCCESS; 84 } 85 86 void imx_cpu_standby(plat_local_state_t cpu_state) 87 { 88 dsb(); 89 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 90 isb(); 91 92 wfi(); 93 94 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); 95 isb(); 96 } 97 98 void imx_domain_suspend(const psci_power_state_t *target_state) 99 { 100 uint64_t base_addr = BL31_BASE; 101 uint64_t mpidr = read_mpidr_el1(); 102 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 103 104 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 105 /* disable the cpu interface */ 106 plat_gic_cpuif_disable(); 107 imx_set_cpu_secure_entry(core_id, base_addr); 108 imx_set_cpu_lpm(core_id, true); 109 } else { 110 dsb(); 111 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 112 isb(); 113 } 114 115 if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) 116 imx_set_cluster_powerdown(core_id, true); 117 else 118 imx_set_cluster_standby(true); 119 120 if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { 121 imx_set_sys_lpm(true); 122 } 123 } 124 125 void imx_domain_suspend_finish(const psci_power_state_t *target_state) 126 { 127 uint64_t mpidr = read_mpidr_el1(); 128 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); 129 130 /* check the system level status */ 131 if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { 132 imx_set_sys_lpm(false); 133 imx_clear_rbc_count(); 134 } 135 136 /* check the cluster level power status */ 137 if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) 138 imx_set_cluster_powerdown(core_id, false); 139 else 140 imx_set_cluster_standby(false); 141 142 /* check the core level power status */ 143 if (is_local_state_off(CORE_PWR_STATE(target_state))) { 144 /* clear the core lpm setting */ 145 imx_set_cpu_lpm(core_id, false); 146 /* enable the gic cpu interface */ 147 plat_gic_cpuif_enable(); 148 } else { 149 write_scr_el3(read_scr_el3() & (~0x4)); 150 isb(); 151 } 152 } 153 154 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) 155 { 156 unsigned int i; 157 158 for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++) 159 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; 160 161 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; 162 } 163 164 void __dead2 imx_system_reset(void) 165 { 166 uintptr_t wdog_base = IMX_WDOG_BASE; 167 unsigned int val; 168 169 /* WDOG_B reset */ 170 val = mmio_read_16(wdog_base); 171 #ifdef IMX_WDOG_B_RESET 172 val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE | 173 WDOG_WCR_WDT | WDOG_WCR_SRS; 174 #else 175 val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS; 176 #endif 177 mmio_write_16(wdog_base, val); 178 179 mmio_write_16(wdog_base + WDOG_WSR, 0x5555); 180 mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa); 181 while (1) 182 ; 183 } 184 185 186 187 void __dead2 imx_system_off(void) 188 { 189 mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV | 190 SNVS_LPCR_DP_EN | SNVS_LPCR_TOP); 191 192 while (1) 193 ; 194 } 195 196 void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 197 { 198 if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) 199 imx_set_rbc_count(); 200 201 while (1) 202 wfi(); 203 } 204 205 static const plat_psci_ops_t imx_plat_psci_ops = { 206 .pwr_domain_on = imx_pwr_domain_on, 207 .pwr_domain_on_finish = imx_pwr_domain_on_finish, 208 .pwr_domain_off = imx_pwr_domain_off, 209 .validate_ns_entrypoint = imx_validate_ns_entrypoint, 210 .validate_power_state = imx_validate_power_state, 211 .cpu_standby = imx_cpu_standby, 212 .pwr_domain_suspend = imx_domain_suspend, 213 .pwr_domain_suspend_finish = imx_domain_suspend_finish, 214 .pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi, 215 .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, 216 .system_reset = imx_system_reset, 217 .system_off = imx_system_off, 218 }; 219 220 /* export the platform specific psci ops */ 221 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 222 const plat_psci_ops_t **psci_ops) 223 { 224 imx_mailbox_init(sec_entrypoint); 225 /* sec_entrypoint is used for warm reset */ 226 *psci_ops = &imx_plat_psci_ops; 227 228 return 0; 229 } 230