| 35988c64 | 13-May-2025 |
Clément Le Goffic <legoffic.clement@gmail.com> |
fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush
Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all the data is out of the shift register.
Change-Id: I
fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush
Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all the data is out of the shift register.
Change-Id: I94b6238e3f8a94bc4a1fabaf8d45d3b66d42e834 Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
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| 5bebf8fe | 13-May-2025 |
Clément Le Goffic <legoffic.clement@gmail.com> |
fix(st-uart): aarch32: remove unnecessary timeout waiting in putc
The UART is configured with FIFO enabled, therefore putting a character in the TDR register and wait for the transmission flag compl
fix(st-uart): aarch32: remove unnecessary timeout waiting in putc
The UART is configured with FIFO enabled, therefore putting a character in the TDR register and wait for the transmission flag complete is enough.
Change-Id: I5e254df89f2652e300ea5bedf9269d420895bdbf Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
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| 65a96c04 | 07-May-2025 |
Clément Le Goffic <legoffic.clement@gmail.com> |
fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush
Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all the data is out of the shift register. Fix the retur
fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush
Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all the data is out of the shift register. Fix the return value that should be void in flush related functions description.
Change-Id: Idbeecc3ca36b6ce506c9489b4f611bbe345121a3 Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
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| ea69dcdc | 13-Sep-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE
If the flag STM32MP_RECONFIGURE_CONSOLE is set in BL32, the UART init should be skipped if the UART clock is set to zero. This will be used when con
feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE
If the flag STM32MP_RECONFIGURE_CONSOLE is set in BL32, the UART init should be skipped if the UART clock is set to zero. This will be used when configuring the default console, after an early console has been configured.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Icbc640c7bdd6342f9c3ec1586a0d0c64127b18b8
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| 1f60d1bd | 28-Feb-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st-uart): manage oversampling by 8
UART oversampling by 8 allows higher baud rates for UART. This is required when (UART freq / baudrate) <= 16. In this case the OVER8 bit needs to be enabled i
feat(st-uart): manage oversampling by 8
UART oversampling by 8 allows higher baud rates for UART. This is required when (UART freq / baudrate) <= 16. In this case the OVER8 bit needs to be enabled in CR1 register. And the BRR register management is different: USARTDIV = (2 * UART freq / baudrate) (with div round nearest) BRR[15:4] = USARTDIV[15:4] BRR[3] = 0 BRR[2:0] = USARTDIV[3:0] >> 1
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ia3fbeeb73a36a4dc485c7ba428c531e65b6f6c09
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