1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <boot_api.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <desc_image_load.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <stm32mp1_clk.h> 20 #include <stm32mp1_dt.h> 21 #include <stm32mp1_private.h> 22 #include <stm32mp1_context.h> 23 #include <stm32mp1_pwr.h> 24 #include <stm32mp1_rcc.h> 25 #include <stm32mp1_reset.h> 26 #include <string.h> 27 #include <xlat_tables_v2.h> 28 29 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 30 u_register_t arg2, u_register_t arg3) 31 { 32 stm32mp1_save_boot_ctx_address(arg0); 33 } 34 35 void bl2_platform_setup(void) 36 { 37 INFO("BL2 runs SP_MIN setup\n"); 38 } 39 40 void bl2_el3_plat_arch_setup(void) 41 { 42 int32_t result; 43 struct dt_node_info dt_dev_info; 44 const char *board_model; 45 boot_api_context_t *boot_context = 46 (boot_api_context_t *)stm32mp1_get_boot_ctx_address(); 47 uint32_t clk_rate; 48 49 /* 50 * Disable the backup domain write protection. 51 * The protection is enable at each reset by hardware 52 * and must be disabled by software. 53 */ 54 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 55 56 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 57 ; 58 } 59 60 /* Reset backup domain on cold boot cases */ 61 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 62 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 63 64 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 65 0U) { 66 ; 67 } 68 69 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 70 } 71 72 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 73 BL_CODE_END - BL_CODE_BASE, 74 MT_CODE | MT_SECURE); 75 76 /* Prevent corruption of preloaded BL32 */ 77 mmap_add_region(BL32_BASE, BL32_BASE, 78 BL32_LIMIT - BL32_BASE, 79 MT_MEMORY | MT_RO | MT_SECURE); 80 81 /* Prevent corruption of preloaded Device Tree */ 82 mmap_add_region(DTB_BASE, DTB_BASE, 83 DTB_LIMIT - DTB_BASE, 84 MT_MEMORY | MT_RO | MT_SECURE); 85 86 configure_mmu(); 87 88 generic_delay_timer_init(); 89 90 if (dt_open_and_check() < 0) { 91 panic(); 92 } 93 94 if (stm32mp1_clk_probe() < 0) { 95 panic(); 96 } 97 98 if (stm32mp1_clk_init() < 0) { 99 panic(); 100 } 101 102 result = dt_get_stdout_uart_info(&dt_dev_info); 103 104 if ((result <= 0) || 105 (dt_dev_info.status == 0U) || 106 (dt_dev_info.clock < 0) || 107 (dt_dev_info.reset < 0)) { 108 goto skip_console_init; 109 } 110 111 if (dt_set_stdout_pinctrl() != 0) { 112 goto skip_console_init; 113 } 114 115 if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) { 116 goto skip_console_init; 117 } 118 119 stm32mp1_reset_assert((uint32_t)dt_dev_info.reset); 120 udelay(2); 121 stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset); 122 mdelay(1); 123 124 clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock); 125 126 if (console_init(dt_dev_info.base, clk_rate, 127 STM32MP1_UART_BAUDRATE) == 0) { 128 panic(); 129 } 130 131 board_model = dt_get_board_model(); 132 if (board_model != NULL) { 133 NOTICE("%s\n", board_model); 134 } 135 136 skip_console_init: 137 138 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 139 boot_context->boot_interface_instance) != 140 0) { 141 ERROR("Cannot save boot interface\n"); 142 } 143 144 stm32mp1_io_setup(); 145 } 146