1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.12 Build 38, unless otherwise stated. 16 17- ``FVP_Base_AEMvA`` 18- ``FVP_Base_AEMv8A-AEMv8A`` 19- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` 20- ``FVP_Base_RevC-2xAEMv8A`` 21- ``FVP_Base_Cortex-A32x4`` 22- ``FVP_Base_Cortex-A35x4`` 23- ``FVP_Base_Cortex-A53x4`` 24- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 25- ``FVP_Base_Cortex-A55x4`` 26- ``FVP_Base_Cortex-A57x1-A53x1`` 27- ``FVP_Base_Cortex-A57x2-A53x4`` 28- ``FVP_Base_Cortex-A57x4-A53x4`` 29- ``FVP_Base_Cortex-A57x4`` 30- ``FVP_Base_Cortex-A65x4`` 31- ``FVP_Base_Cortex-A65AEx8`` 32- ``FVP_Base_Cortex-A72x4-A53x4`` 33- ``FVP_Base_Cortex-A72x4`` 34- ``FVP_Base_Cortex-A73x4-A53x4`` 35- ``FVP_Base_Cortex-A73x4`` 36- ``FVP_Base_Cortex-A75x4`` 37- ``FVP_Base_Cortex-A76x4`` 38- ``FVP_Base_Cortex-A76AEx4`` 39- ``FVP_Base_Cortex-A76AEx8`` 40- ``FVP_Base_Cortex-A77x4`` 41- ``FVP_Base_Cortex-A78x4`` 42- ``FVP_Base_Neoverse-E1x1`` 43- ``FVP_Base_Neoverse-E1x2`` 44- ``FVP_Base_Neoverse-E1x4`` 45- ``FVP_Base_Neoverse-N1x4`` 46- ``FVP_Base_Neoverse-V1x4`` 47- ``FVP_CSS_SGI-575`` (Version 11.10 build 36) 48- ``FVP_CSS_SGM-775`` 49- ``FVP_RD_E1_edge`` (Version 11.9 build 41) 50- ``FVP_RD_N1_edge`` (Version 11.10 build 36) 51- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) 52- ``FVP_RD_Daniel`` (Version 11.10 build 36) 53- ``FVP_TC0`` (Version 0.0 build 6114) 54- ``Foundation_Platform`` 55 56The latest version of the AArch32 build of TF-A has been tested on the 57following Arm FVPs without shifted affinities, and that do not support threaded 58CPU cores (64-bit host machine only). 59 60- ``FVP_Base_AEMvA`` 61- ``FVP_Base_AEMv8A-AEMv8A`` 62- ``FVP_Base_Cortex-A32x4`` 63 64.. note:: 65 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which 66 is not compatible with legacy GIC configurations. Therefore this FVP does not 67 support these legacy GIC configurations. 68 69The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 70FVP website`_. The Cortex-A models listed above are also available to download 71from `Arm's website`_. 72 73.. note:: 74 The build numbers quoted above are those reported by launching the FVP 75 with the ``--version`` parameter. 76 77.. note:: 78 Linaro provides a ramdisk image in prebuilt FVP configurations and full 79 file systems that can be downloaded separately. To run an FVP with a virtio 80 file system image an additional FVP configuration option 81 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 82 used. 83 84.. note:: 85 The software will not work on Version 1.0 of the Foundation FVP. 86 The commands below would report an ``unhandled argument`` error in this case. 87 88.. note:: 89 FVPs can be launched with ``--cadi-server`` option such that a 90 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 91 its execution. 92 93.. warning:: 94 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 95 the internal synchronisation timings changed compared to older versions of 96 the models. The models can be launched with ``-Q 100`` option if they are 97 required to match the run time characteristics of the older versions. 98 99All the above platforms have been tested with `Linaro Release 19.06`_. 100 101.. _build_options_arm_fvp_platform: 102 103Arm FVP Platform Specific Build Options 104--------------------------------------- 105 106- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 107 build the topology tree within TF-A. By default TF-A is configured for dual 108 cluster topology and this option can be used to override the default value. 109 110- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 111 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 112 explained in the options below: 113 114 - ``FVP_CCI`` : The CCI driver is selected. This is the default 115 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 116 - ``FVP_CCN`` : The CCN driver is selected. This is the default 117 if ``FVP_CLUSTER_COUNT`` > 2. 118 119- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 120 a single cluster. This option defaults to 4. 121 122- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 123 in the system. This option defaults to 1. Note that the build option 124 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 125 126- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 127 128 - ``FVP_GICV2`` : The GICv2 only driver is selected 129 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 130 131- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 132 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 133 details on HW_CONFIG. By default, this is initialized to a sensible DTS 134 file in ``fdts/`` folder depending on other build options. But some cases, 135 like shifted affinity format for MPIDR, cannot be detected at build time 136 and this option is needed to specify the appropriate DTS file. 137 138- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 139 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 140 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 141 HW_CONFIG blob instead of the DTS file. This option is useful to override 142 the default HW_CONFIG selected by the build system. 143 144Booting Firmware Update images 145------------------------------ 146 147When Firmware Update (FWU) is enabled there are at least 2 new images 148that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 149FWU FIP. 150 151The additional fip images must be loaded with: 152 153:: 154 155 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 156 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 157 158The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 159In the same way, the address ns_bl2u_base_address is the value of 160NS_BL2U_BASE. 161 162Booting an EL3 payload 163---------------------- 164 165The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 166the secondary CPUs holding pen to work properly. Unfortunately, its reset value 167is undefined on the FVP platform and the FVP platform code doesn't clear it. 168Therefore, one must modify the way the model is normally invoked in order to 169clear the mailbox at start-up. 170 171One way to do that is to create an 8-byte file containing all zero bytes using 172the following command: 173 174.. code:: shell 175 176 dd if=/dev/zero of=mailbox.dat bs=1 count=8 177 178and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 179using the following model parameters: 180 181:: 182 183 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 184 --data=mailbox.dat@0x04000000 [Foundation FVP] 185 186To provide the model with the EL3 payload image, the following methods may be 187used: 188 189#. If the EL3 payload is able to execute in place, it may be programmed into 190 flash memory. On Base Cortex and AEM FVPs, the following model parameter 191 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 192 used for the FIP): 193 194 :: 195 196 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 197 198 On Foundation FVP, there is no flash loader component and the EL3 payload 199 may be programmed anywhere in flash using method 3 below. 200 201#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 202 command may be used to load the EL3 payload ELF image over JTAG: 203 204 :: 205 206 load <path-to>/el3-payload.elf 207 208#. The EL3 payload may be pre-loaded in volatile memory using the following 209 model parameters: 210 211 :: 212 213 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 214 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 215 216 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 217 used when building TF-A. 218 219Booting a preloaded kernel image (Base FVP) 220------------------------------------------- 221 222The following example uses a simplified boot flow by directly jumping from the 223TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 224useful if both the kernel and the device tree blob (DTB) are already present in 225memory (like in FVP). 226 227For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 228address ``0x82000000``, the firmware can be built like this: 229 230.. code:: shell 231 232 CROSS_COMPILE=aarch64-none-elf- \ 233 make PLAT=fvp DEBUG=1 \ 234 RESET_TO_BL31=1 \ 235 ARM_LINUX_KERNEL_AS_BL33=1 \ 236 PRELOADED_BL33_BASE=0x80080000 \ 237 ARM_PRELOADED_DTB_BASE=0x82000000 \ 238 all fip 239 240Now, it is needed to modify the DTB so that the kernel knows the address of the 241ramdisk. The following script generates a patched DTB from the provided one, 242assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 243script assumes that the user is using a ramdisk image prepared for U-Boot, like 244the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 245offset in ``INITRD_START`` has to be removed. 246 247.. code:: bash 248 249 #!/bin/bash 250 251 # Path to the input DTB 252 KERNEL_DTB=<path-to>/<fdt> 253 # Path to the output DTB 254 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 255 # Base address of the ramdisk 256 INITRD_BASE=0x84000000 257 # Path to the ramdisk 258 INITRD=<path-to>/<ramdisk.img> 259 260 # Skip uboot header (64 bytes) 261 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 262 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 263 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 264 265 CHOSEN_NODE=$(echo \ 266 "/ { \ 267 chosen { \ 268 linux,initrd-start = <${INITRD_START}>; \ 269 linux,initrd-end = <${INITRD_END}>; \ 270 }; \ 271 };") 272 273 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 274 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 275 276And the FVP binary can be run with the following command: 277 278.. code:: shell 279 280 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 281 -C pctl.startup=0.0.0.0 \ 282 -C bp.secure_memory=1 \ 283 -C cluster0.NUM_CORES=4 \ 284 -C cluster1.NUM_CORES=4 \ 285 -C cache_state_modelled=1 \ 286 -C cluster0.cpu0.RVBAR=0x04001000 \ 287 -C cluster0.cpu1.RVBAR=0x04001000 \ 288 -C cluster0.cpu2.RVBAR=0x04001000 \ 289 -C cluster0.cpu3.RVBAR=0x04001000 \ 290 -C cluster1.cpu0.RVBAR=0x04001000 \ 291 -C cluster1.cpu1.RVBAR=0x04001000 \ 292 -C cluster1.cpu2.RVBAR=0x04001000 \ 293 -C cluster1.cpu3.RVBAR=0x04001000 \ 294 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 295 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 296 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 297 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 298 299Obtaining the Flattened Device Trees 300^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 301 302Depending on the FVP configuration and Linux configuration used, different 303FDT files are required. FDT source files for the Foundation and Base FVPs can 304be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 305a subset of the Base FVP components. For example, the Foundation FVP lacks 306CLCD and MMC support, and has only one CPU cluster. 307 308.. note:: 309 It is not recommended to use the FDTs built along the kernel because not 310 all FDTs are available from there. 311 312The dynamic configuration capability is enabled in the firmware for FVPs. 313This means that the firmware can authenticate and load the FDT if present in 314FIP. A default FDT is packaged into FIP during the build based on 315the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 316or ``FVP_HW_CONFIG_DTS`` build options (refer to 317:ref:`build_options_arm_fvp_platform` for details on the options). 318 319- ``fvp-base-gicv2-psci.dts`` 320 321 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 322 affinities and with Base memory map configuration. 323 324- ``fvp-base-gicv2-psci-aarch32.dts`` 325 326 For use with models such as the Cortex-A32 Base FVPs without shifted 327 affinities and running Linux in AArch32 state with Base memory map 328 configuration. 329 330- ``fvp-base-gicv3-psci.dts`` 331 332 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 333 affinities and with Base memory map configuration and Linux GICv3 support. 334 335- ``fvp-base-gicv3-psci-1t.dts`` 336 337 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 338 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 339 340- ``fvp-base-gicv3-psci-dynamiq.dts`` 341 342 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 343 single cluster, single threaded CPUs, Base memory map configuration and Linux 344 GICv3 support. 345 346- ``fvp-base-gicv3-psci-aarch32.dts`` 347 348 For use with models such as the Cortex-A32 Base FVPs without shifted 349 affinities and running Linux in AArch32 state with Base memory map 350 configuration and Linux GICv3 support. 351 352- ``fvp-foundation-gicv2-psci.dts`` 353 354 For use with Foundation FVP with Base memory map configuration. 355 356- ``fvp-foundation-gicv3-psci.dts`` 357 358 (Default) For use with Foundation FVP with Base memory map configuration 359 and Linux GICv3 support. 360 361 362Running on the Foundation FVP with reset to BL1 entrypoint 363^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 364 365The following ``Foundation_Platform`` parameters should be used to boot Linux with 3664 CPUs using the AArch64 build of TF-A. 367 368.. code:: shell 369 370 <path-to>/Foundation_Platform \ 371 --cores=4 \ 372 --arm-v8.0 \ 373 --secure-memory \ 374 --visualization \ 375 --gicv3 \ 376 --data="<path-to>/<bl1-binary>"@0x0 \ 377 --data="<path-to>/<FIP-binary>"@0x08000000 \ 378 --data="<path-to>/<kernel-binary>"@0x80080000 \ 379 --data="<path-to>/<ramdisk-binary>"@0x84000000 380 381Notes: 382 383- BL1 is loaded at the start of the Trusted ROM. 384- The Firmware Image Package is loaded at the start of NOR FLASH0. 385- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 386 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. 387- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 388 and enable the GICv3 device in the model. Note that without this option, 389 the Foundation FVP defaults to legacy (Versatile Express) memory map which 390 is not supported by TF-A. 391- In order for TF-A to run correctly on the Foundation FVP, the architecture 392 versions must match. The Foundation FVP defaults to the highest v8.x 393 version it supports but the default build for TF-A is for v8.0. To avoid 394 issues either start the Foundation FVP to use v8.0 architecture using the 395 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 396 ``ARM_ARCH_MINOR``. 397 398Running on the AEMv8 Base FVP with reset to BL1 entrypoint 399^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 400 401The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 402with 8 CPUs using the AArch64 build of TF-A. 403 404.. code:: shell 405 406 <path-to>/FVP_Base_RevC-2xAEMv8A \ 407 -C pctl.startup=0.0.0.0 \ 408 -C bp.secure_memory=1 \ 409 -C bp.tzc_400.diagnostics=1 \ 410 -C cluster0.NUM_CORES=4 \ 411 -C cluster1.NUM_CORES=4 \ 412 -C cache_state_modelled=1 \ 413 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 414 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 415 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 416 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 417 418.. note:: 419 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 420 a specific DTS for all the CPUs to be loaded. 421 422Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 423^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 424 425The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 426with 8 CPUs using the AArch32 build of TF-A. 427 428.. code:: shell 429 430 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 431 -C pctl.startup=0.0.0.0 \ 432 -C bp.secure_memory=1 \ 433 -C bp.tzc_400.diagnostics=1 \ 434 -C cluster0.NUM_CORES=4 \ 435 -C cluster1.NUM_CORES=4 \ 436 -C cache_state_modelled=1 \ 437 -C cluster0.cpu0.CONFIG64=0 \ 438 -C cluster0.cpu1.CONFIG64=0 \ 439 -C cluster0.cpu2.CONFIG64=0 \ 440 -C cluster0.cpu3.CONFIG64=0 \ 441 -C cluster1.cpu0.CONFIG64=0 \ 442 -C cluster1.cpu1.CONFIG64=0 \ 443 -C cluster1.cpu2.CONFIG64=0 \ 444 -C cluster1.cpu3.CONFIG64=0 \ 445 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 446 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 447 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 448 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 449 450Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 451^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 452 453The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 454boot Linux with 8 CPUs using the AArch64 build of TF-A. 455 456.. code:: shell 457 458 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 459 -C pctl.startup=0.0.0.0 \ 460 -C bp.secure_memory=1 \ 461 -C bp.tzc_400.diagnostics=1 \ 462 -C cache_state_modelled=1 \ 463 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 464 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 465 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 466 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 467 468Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 469^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 470 471The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 472boot Linux with 4 CPUs using the AArch32 build of TF-A. 473 474.. code:: shell 475 476 <path-to>/FVP_Base_Cortex-A32x4 \ 477 -C pctl.startup=0.0.0.0 \ 478 -C bp.secure_memory=1 \ 479 -C bp.tzc_400.diagnostics=1 \ 480 -C cache_state_modelled=1 \ 481 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 482 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 483 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 484 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 485 486 487Running on the AEMv8 Base FVP with reset to BL31 entrypoint 488^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 489 490The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 491with 8 CPUs using the AArch64 build of TF-A. 492 493.. code:: shell 494 495 <path-to>/FVP_Base_RevC-2xAEMv8A \ 496 -C pctl.startup=0.0.0.0 \ 497 -C bp.secure_memory=1 \ 498 -C bp.tzc_400.diagnostics=1 \ 499 -C cluster0.NUM_CORES=4 \ 500 -C cluster1.NUM_CORES=4 \ 501 -C cache_state_modelled=1 \ 502 -C cluster0.cpu0.RVBAR=0x04010000 \ 503 -C cluster0.cpu1.RVBAR=0x04010000 \ 504 -C cluster0.cpu2.RVBAR=0x04010000 \ 505 -C cluster0.cpu3.RVBAR=0x04010000 \ 506 -C cluster1.cpu0.RVBAR=0x04010000 \ 507 -C cluster1.cpu1.RVBAR=0x04010000 \ 508 -C cluster1.cpu2.RVBAR=0x04010000 \ 509 -C cluster1.cpu3.RVBAR=0x04010000 \ 510 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 511 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 512 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 513 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 514 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 515 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 516 517Notes: 518 519- If Position Independent Executable (PIE) support is enabled for BL31 520 in this config, it can be loaded at any valid address for execution. 521 522- Since a FIP is not loaded when using BL31 as reset entrypoint, the 523 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 524 parameter is needed to load the individual bootloader images in memory. 525 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 526 Payload. For the same reason, the FDT needs to be compiled from the DT source 527 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 528 parameter. 529 530- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 531 specific DTS for all the CPUs to be loaded. 532 533- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 534 X and Y are the cluster and CPU numbers respectively, is used to set the 535 reset vector for each core. 536 537- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 538 changing the value of 539 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 540 ``BL32_BASE``. 541 542 543Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 544^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 545 546The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 547with 8 CPUs using the AArch32 build of TF-A. 548 549.. code:: shell 550 551 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 552 -C pctl.startup=0.0.0.0 \ 553 -C bp.secure_memory=1 \ 554 -C bp.tzc_400.diagnostics=1 \ 555 -C cluster0.NUM_CORES=4 \ 556 -C cluster1.NUM_CORES=4 \ 557 -C cache_state_modelled=1 \ 558 -C cluster0.cpu0.CONFIG64=0 \ 559 -C cluster0.cpu1.CONFIG64=0 \ 560 -C cluster0.cpu2.CONFIG64=0 \ 561 -C cluster0.cpu3.CONFIG64=0 \ 562 -C cluster1.cpu0.CONFIG64=0 \ 563 -C cluster1.cpu1.CONFIG64=0 \ 564 -C cluster1.cpu2.CONFIG64=0 \ 565 -C cluster1.cpu3.CONFIG64=0 \ 566 -C cluster0.cpu0.RVBAR=0x04002000 \ 567 -C cluster0.cpu1.RVBAR=0x04002000 \ 568 -C cluster0.cpu2.RVBAR=0x04002000 \ 569 -C cluster0.cpu3.RVBAR=0x04002000 \ 570 -C cluster1.cpu0.RVBAR=0x04002000 \ 571 -C cluster1.cpu1.RVBAR=0x04002000 \ 572 -C cluster1.cpu2.RVBAR=0x04002000 \ 573 -C cluster1.cpu3.RVBAR=0x04002000 \ 574 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 575 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 576 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 577 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 578 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 579 580.. note:: 581 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. 582 It should match the address programmed into the RVBAR register as well. 583 584Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 585^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 586 587The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 588boot Linux with 8 CPUs using the AArch64 build of TF-A. 589 590.. code:: shell 591 592 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 593 -C pctl.startup=0.0.0.0 \ 594 -C bp.secure_memory=1 \ 595 -C bp.tzc_400.diagnostics=1 \ 596 -C cache_state_modelled=1 \ 597 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 598 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 599 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 600 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 601 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 602 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 603 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 604 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 605 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 606 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 607 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 608 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 609 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 610 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 611 612Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 613^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 614 615The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 616boot Linux with 4 CPUs using the AArch32 build of TF-A. 617 618.. code:: shell 619 620 <path-to>/FVP_Base_Cortex-A32x4 \ 621 -C pctl.startup=0.0.0.0 \ 622 -C bp.secure_memory=1 \ 623 -C bp.tzc_400.diagnostics=1 \ 624 -C cache_state_modelled=1 \ 625 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 626 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 627 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 628 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 629 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 630 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 631 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 632 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 633 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 634 635-------------- 636 637*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 638 639.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts 640.. _Arm's website: `FVP models`_ 641.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 642.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 643.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 644