1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <boot_api.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <desc_image_load.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <stm32mp1_private.h> 20 #include <stm32mp1_pwr.h> 21 #include <stm32mp1_rcc.h> 22 #include <string.h> 23 #include <xlat_tables_v2.h> 24 25 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 26 u_register_t arg2, u_register_t arg3) 27 { 28 stm32mp1_save_boot_ctx_address(arg0); 29 } 30 31 void bl2_platform_setup(void) 32 { 33 INFO("BL2 runs SP_MIN setup\n"); 34 } 35 36 void bl2_el3_plat_arch_setup(void) 37 { 38 /* 39 * Disable the backup domain write protection. 40 * The protection is enable at each reset by hardware 41 * and must be disabled by software. 42 */ 43 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 44 45 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 46 ; 47 } 48 49 /* Reset backup domain on cold boot cases */ 50 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 51 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 52 53 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 54 0U) { 55 ; 56 } 57 58 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 59 } 60 61 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 62 BL_CODE_END - BL_CODE_BASE, 63 MT_CODE | MT_SECURE); 64 65 /* Prevent corruption of preloaded BL32 */ 66 mmap_add_region(BL32_BASE, BL32_BASE, 67 BL32_LIMIT - BL32_BASE, 68 MT_MEMORY | MT_RO | MT_SECURE); 69 70 /* Prevent corruption of preloaded Device Tree */ 71 mmap_add_region(DTB_BASE, DTB_BASE, 72 DTB_LIMIT - DTB_BASE, 73 MT_MEMORY | MT_RO | MT_SECURE); 74 75 configure_mmu(); 76 77 generic_delay_timer_init(); 78 79 stm32mp1_io_setup(); 80 } 81