imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct th

imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Reg

imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Register which comes in a quadrumvirate
register set to read, set, clear and toggle individual clock gates into
one of four states based bitmask.

00: Domain clocks not needed
01: Domain clocks needed when in RUN
10: Domain clocks needed when in RUN and WAIT
11: Domain clocks needed all the time

- Defines clock control register bits

There are various quadrumvirate register blocks target-root, misc-root,
post-root, pre-root in the CCM.

The number of registers is huge but the four registers in each
quadrumvirate block contain the same bits, so the number of bit
definitions is actually quite low.

- Defines clock identifiers

An array of clock gates is provided in the CCM block. In order to index
that array and thus enable/disable clock gates for the right components,
we need to provide meaningful names to the indices.

Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual
Rev 0.1 provides the relevant details.

- Defines target mux select bits
This is a comprehensive definition of the target clock mux select bits.
These bits are required to correctly select the clock source. Defining
all of the bits up-front even for unused blocks in ATF means we can
switch on any block we want at a later date without having to write new
code in the clock-mux layer.

- Defines identifier indices into root-slice array
The root-slice array of control registers has a specific set of indices,
which differ from the clock-gate indices.

- Provides a clock gate enable/disable routine
Provides a clock-gate enable/disable routine via the set/clr
registers in a given clock-gate control register block.

This index passed should be one of the enums associated with CCM and
depending on enable/disable being passed either set or clr will be
written to.

The Domain0 bits are currently the only bits targeted by this write, more
work may need to be done on the domain bits in subsequent patches as a
result.

- imx: Adds set/clr routines to clock layer

Adds a set and clr routine to the clock layer. These routines allow us to
access the set and clear registers of the "target" block registers. These
are the registers where we select the clock source from the available list.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

libc: Fix all includes in codebase

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb03

libc: Fix all includes in codebase

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

imx: imx8qx: add domain suspend/resume support

Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered

imx: imx8qx: add domain suspend/resume support

Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered off and can be waked up if irq pending
in GIC, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

show more ...

imx: imx8qx: add system reset support

Add system reset support for i.MX8QX,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board accordi

imx: imx8qx: add system reset support

Add system reset support for i.MX8QX,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board according
to board design, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

show more ...

imx: imx8qx: add system off support

Add system power off support for i.MX8QX,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board

imx: imx8qx: add system off support

Add system power off support for i.MX8QX,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board according
to board design, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

show more ...

Support for NXP's i.MX8QM SoC

NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72
cores in one cluster and 4 Cortex-A53 in the other cluster,
and also has system controller (Cortex-M4) insid

Support for NXP's i.MX8QM SoC

NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72
cores in one cluster and 4 Cortex-A53 in the other cluster,
and also has system controller (Cortex-M4) inside, documentation
can be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

show more ...

Support for NXP's i.MX8QX SoC

NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and
system controller (Cortex-M4) inside, documentation can
be found in below link:

https://www.nxp.com/products/

Support for NXP's i.MX8QX SoC

NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and
system controller (Cortex-M4) inside, documentation can
be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

show more ...

Support for NXP's imx SoC common function

This patch adds support for NXP's imx SoC common
function support like topology, gic implementation.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's imx SoC debug uart

Add NXP's imx SoC debug uart driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's i.MX8 SoCs IPC

NXP's i.MX8 SoCs have system controller (M4 core)
which takes control of clock management, power management,
partition management, PAD management etc., other
cluster

Support for NXP's i.MX8 SoCs IPC

NXP's i.MX8 SoCs have system controller (M4 core)
which takes control of clock management, power management,
partition management, PAD management etc., other
clusters like Cortex-A35 can send out command via MU
(Message Unit) to system controller for clock/power
management etc..

This patch adds basic IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

show more ...