1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 11 #define PLATFORM_LINKER_ARCH aarch64 12 13 #define PLATFORM_STACK_SIZE 0x400 14 #define CACHE_WRITEBACK_GRANULE 64 15 16 #define PLAT_PRIMARY_CPU 0x0 17 #define PLATFORM_MAX_CPU_PER_CLUSTER 4 18 #define PLATFORM_CLUSTER_COUNT 1 19 #define PLATFORM_CORE_COUNT 4 20 21 #define PWR_DOMAIN_AT_MAX_LVL 1 22 #define PLAT_MAX_PWR_LVL 2 23 #define PLAT_MAX_OFF_STATE 2 24 #define PLAT_MAX_RET_STATE 1 25 26 #define BL31_BASE 0x80000000 27 #define BL31_LIMIT 0x80020000 28 29 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 30 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 31 32 #define MAX_XLAT_TABLES 8 33 #define MAX_MMAP_REGIONS 8 34 35 #define PLAT_GICD_BASE 0x51a00000 36 #define PLAT_GICD_SIZE 0x10000 37 #define PLAT_GICR_BASE 0x51b00000 38 #define PLAT_GICR_SIZE 0xc0000 39 #define IMX_BOOT_UART_BASE 0x5a060000 40 #define IMX_BOOT_UART_SIZE 0x1000 41 #define IMX_BOOT_UART_BAUDRATE 115200 42 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 43 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 44 #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 45 #define IMX_CONSOLE_BAUDRATE 115200 46 #define SC_IPC_BASE 0x5d1b0000 47 #define SC_IPC_SIZE 0x10000 48 49 #define COUNTER_FREQUENCY 8000000 50 51 /* non-secure u-boot base */ 52 #define PLAT_NS_IMAGE_OFFSET 0x80020000 53 54 #define DEBUG_CONSOLE 0 55 #define DEBUG_CONSOLE_A35 0 56 #define PLAT_IMX8QX 1 57 58 #endif /* __PLATFORM_DEF_H__ */ 59