1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <debug.h> 10 #include <gicv3.h> 11 #include <mmio.h> 12 #include <plat_imx8.h> 13 #include <psci.h> 14 #include <sci/sci.h> 15 #include <stdbool.h> 16 17 const static int ap_core_index[PLATFORM_CORE_COUNT] = { 18 SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3 19 }; 20 21 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, 22 const plat_local_state_t *target_state, 23 unsigned int ncpu) 24 { 25 return 0; 26 } 27 28 int imx_pwr_domain_on(u_register_t mpidr) 29 { 30 int ret = PSCI_E_SUCCESS; 31 unsigned int cpu_id; 32 33 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 34 35 tf_printf("imx_pwr_domain_on cpu_id %d\n", cpu_id); 36 37 if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], 38 SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 39 ERROR("core %d power on failed!\n", cpu_id); 40 ret = PSCI_E_INTERN_FAIL; 41 } 42 43 if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], 44 true, BL31_BASE) != SC_ERR_NONE) { 45 ERROR("boot core %d failed!\n", cpu_id); 46 ret = PSCI_E_INTERN_FAIL; 47 } 48 49 return ret; 50 } 51 52 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 53 { 54 plat_gic_pcpu_init(); 55 plat_gic_cpuif_enable(); 56 } 57 58 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 59 { 60 return PSCI_E_SUCCESS; 61 } 62 63 static const plat_psci_ops_t imx_plat_psci_ops = { 64 .pwr_domain_on = imx_pwr_domain_on, 65 .pwr_domain_on_finish = imx_pwr_domain_on_finish, 66 .validate_ns_entrypoint = imx_validate_ns_entrypoint, 67 }; 68 69 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 70 const plat_psci_ops_t **psci_ops) 71 { 72 imx_mailbox_init(sec_entrypoint); 73 *psci_ops = &imx_plat_psci_ops; 74 75 return 0; 76 } 77