feat(imx9): add necessary ele api call support

Add the soc info and release xspi gmid ELE API call support.

Also add soc id sip call support. we need to flush the soc info buffer
address range to m

feat(imx9): add necessary ele api call support

Add the soc info and release xspi gmid ELE API call support.

Also add soc id sip call support. we need to flush the soc info buffer
address range to make sure no stolen data in the cache as the ELE will
fill the data without coherance support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3d486902960fe39bdfe810f0d0c8ee75bae6fcc5

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refactor(imx): drop the __dead2 attribute

Drop the __dead2 attribute to make sure these functions can be
implemented as no dead.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I93129cdc6dae

refactor(imx): drop the __dead2 attribute

Drop the __dead2 attribute to make sure these functions can be
implemented as no dead.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I93129cdc6daea494ac5dd6868a05d97eaf1a610c

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fix(imx8mq): fix imx8mq build break due to hab

Add the HAB secure boot support for the i.MX8MQ to
fix the build break.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I806de2dc42806e008355cc

fix(imx8mq): fix imx8mq build break due to hab

Add the HAB secure boot support for the i.MX8MQ to
fix the build break.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I806de2dc42806e008355cc185065e774570362f0

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fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no long

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no longer
fit On-Chip SRAM.

In order to make the i.MX8MQ Image buildable again, let's make the DRAM
retention feature optional: It was added in v2.9 and it's possible to
boot the systems without it. Users that make space elsewhere and wish to
enable it can use the newly introduced IMX_DRAM_RETENTION parameter to
configure it. The parameter is added to all i.MX8M variants, but only
for i.MX8MQ, we disable it by default, as that's the one that currently
has binary size problems.

Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7
Fixes: dd108c3c1fe3 ("feat(imx8mq): add the dram retention support for imx8mq")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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feat(imx): add helper to take params from BL2

So far the i.MX BL31 doesn't take any parameters. This means the BL32
image base address and whether or not a BL32 image is used at all has to
be hardco

feat(imx): add helper to take params from BL2

So far the i.MX BL31 doesn't take any parameters. This means the BL32
image base address and whether or not a BL32 image is used at all has to
be hardcoded in BL31.

This adds a helper function that allows to take params from BL2 safely.
On i.MX BL2 is usually U-Boot SPL which passes random values in arg0,
so make sure arg0 is within the internal SRAM range before accessing it
as a pointer. Also make sure arg0 is sufficiently aligned and the header
type and version is correct.

Change-Id: Idab8013a1d6dabf50a83c75f3e6f831de4a537e9
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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feat(imx8ulp): enable the DDR frequency scaling support

Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:

0: boot frequency;
1: low frequency(PLL

feat(imx8ulp): enable the DDR frequency scaling support

Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:

0: boot frequency;
1: low frequency(PLL bypassed);
2. high frequency(PLL ON).

Currently, DDR DFS only do frequency switching between
Low freq and high freq.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I3acd8bdf75e2dd6dff645b9f597dcfc0a756c428

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feat(imx8ulp): add the initial XRDC support

Add the initial xRDC support on i.MX8ULP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.

feat(imx8ulp): add the initial XRDC support

Add the initial xRDC support on i.MX8ULP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I93ea8e2cebb049e6f20e71cfe50c7583a3228f38

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feat(imx8ulp): add i.MX8ULP basic support

Add the basic support for i.MX8ULP.

The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an

feat(imx8ulp): add i.MX8ULP basic support

Add the basic support for i.MX8ULP.

The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an Arm Cortex-M33. This combined architecture enables the
device to run a rich operating system (such as Linux) on
the Cortex-A35 core and an RTOS (such as FreeRTOS) on the
Cortex-M33 core. It also includes a Cadence Tensilica Fusion
DSP for low-power audio and a HiFi4 DSP for advanced audio
and machine learning applications.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36

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feat(imx8m): obtain boot image set for imx8mn/mp

In i.MX8MM/MQ it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in ca

feat(imx8m): obtain boot image set for imx8mn/mp

In i.MX8MM/MQ it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in case the bootloader image is faulty OR can be
enforced by the user, and there is API introduced in
9ce232fe ("feat(plat/imx8m): add SiP call for secondary boot"),
which leverages this SoC feature.

However neither i.MX8MP nor i.MX8MN have a dedicated bit
which indicates what boot image set is currently booted.
According to AN12853 [1] "i.MX ROMs Log Events", it is
possible to determine whether fallback event occurred
by parsing the BootROM event log. In case ROM event ID 0x51 is
present,fallback event did occur and secondary boot image was booted.

Knowing which boot image was booted might be useful for reliable
bootloader A/B updates, detecting fallback event might be used for
making decision if boot firmware rollback is required.

This patche introduces implementation, that replicates the same
imx_src_handler() behaviour as on i.MX8MM/MQ SoCs.

The code is based on original U-Boot implementation [2].

[1]: https://www.nxp.com/webapp/Download?colCode=AN12853
[2]: https://github.com/u-boot/u-boot/commit/a5ee05cf7180b411ffdf148ca8cb220c029f2e19

Change-Id: I9a4c5229aa0e53fa23b5261459da99cb3ce6bdbe
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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