| be48511e | 04-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Reimplement clock set parent EEMI API
Clock set parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll
zynqmp: pm: Reimplement clock set parent EEMI API
Clock set parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to set pre_src, post_src, div2
and bypass, in the implementation of pm_clock_set_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly
an on-chip clock.
For case 1) we'll map the call onto PLL set parameter EEMI API with the
respective parameter ID. Since clock set parent interface to EL1/2 receives
parent index (mux select value), the value is just passed to PMU.
Functions that appear to be unused after this change is made are removed.
Setting the parent of *PLL clocks, that actually model bypass, is not
possible. This is already ensured by the existing clock model having the
CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the
bypass parent. Bypass is controlled only by the PMU firmware.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 8bc945fb | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Cleanup for clock set/get rate EEMI API
Clock set/get rate are not implemented and will likely never be.
Remove empty function stubs.
Signed-off-by: Mirela Simonovic <mirela.simonovic@a
zynqmp: pm: Cleanup for clock set/get rate EEMI API
Clock set/get rate are not implemented and will likely never be.
Remove empty function stubs.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| b071dcd9 | 04-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Reimplement clock get divider EEMI API
Clock get divider EEMI API is reimplemented to use system-level clock
get divider EEMI API rather than direct MMIO read/write accesses to clock
con
zynqmp: pm: Reimplement clock get divider EEMI API
Clock get divider EEMI API is reimplemented to use system-level clock
get divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 48dc44e3 | 04-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Reimplement clock set divider EEMI API
Clock set divider EEMI API is reimplemented to use system-level clock
set divider EEMI API rather than direct MMIO read/write accesses to clock
con
zynqmp: pm: Reimplement clock set divider EEMI API
Clock set divider EEMI API is reimplemented to use system-level clock
set divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| bd30503a | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Reimplement clock get state (status) EEMI API
Clock get state EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
a
zynqmp: pm: Reimplement clock get state (status) EEMI API
Clock get state EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux is_enabled method for PLLs still uses clock get state API
get the PLL state, in the implementation of pm_clock_getstate() we need
to workaround this by distinguishing two cases: 1) if the given clock ID
corresponds to a PLL output clock ID; or 2) given clock ID is truly an
on-chip clock whose state of the gate should be returned.
For case 1) we'll call pm_api_clock_pll_getstate() implemented in
pm_api_clock.h/c. This function will query the PLL state from PMU using
the system-level PLL get mode EEMI API.
For case 2) we'll call the PMU to query the clock gate state using
system-level clock get status EEMI API.
Functions that appear to be unused after this change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| d3a78ca4 | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Reimplement clock disable EEMI API
Clock disable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll contro
zynqmp: pm: Reimplement clock disable EEMI API
Clock disable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock disable API to reset the PLL in the
implementation of pm_clock_disable() we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_disable() implemented in
pm_api_clock.h/c. This function will reset the PLL using the system-level
PLL set mode EEMI API with the reset mode argument.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock disable EEMI API.
Functions that appear to be unused after this change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| bd642dde | 04-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Reimplement clock enable EEMI API
Clock enable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control
zynqmp: pm: Reimplement clock enable EEMI API
Clock enable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock enable API to trigger locking of the PLLs
in the pm_clock_enable() implementation we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_enable() implemented in
pm_api_clock.h/c. This function checks what is the buffered PLL mode and
calls the system-level PLL set mode EEMI API with the buffered mode value
specified as argument. Long term, if linux driver get fixed to use PLL
EEMI API to control PLLs, this case could be removed from ATF.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock enable EEMI API.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| a5ae5a72 | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Return the buffered PLL mode through IOCTL PLL get mode API
When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual
mode to be read from hardware, but the value that i
zynqmp: pm: Return the buffered PLL mode through IOCTL PLL get mode API
When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual
mode to be read from hardware, but the value that it is intending to
program. Therefore, we return the buffered value to linux.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 8975f317 | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Buffer the PLL mode that is set using IOCTL API
When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before th
zynqmp: pm: Buffer the PLL mode that is set using IOCTL API
When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before this
patch setting the mode which is done by writing into register takes
no effect until the PLL reset is deasserted, i.e. until linux "enables"
the PLL. To adjust the code to system-level PLL EEMI API and avoid
unnecessary IPIs that would otherwise be issued, we buffer the mode
value set via IOCTL until the PLL mode really needs to be set.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| cf1769b5 | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Set PLL fractional data using PLL set parameter EEMI API
Fractional data should be set using PLL set parameter EEMI API. This
stands for system-level communication (APU to PMU). Since li
zynqmp: pm: Set PLL fractional data using PLL set parameter EEMI API
Fractional data should be set using PLL set parameter EEMI API. This
stands for system-level communication (APU to PMU). Since linux
already uses a specific IOCTL function to do this and we need to
keep it that way, the pll clock ID given by linux has to be mapped
to the pll node ID that is communicated at the system-level (argument
of PLL set parameter API).
With this modification the function pm_api_clk_set_pll_frac_data is
removed from pm_api_clock.c/h because it became unused.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 1e3fb352 | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Get PLL fractional data using PLL get parameter EEMI API
Fractional data should be get using PLL get parameter EEMI API. This
stands for system-level communication (APU to PMU). Since li
zynqmp: pm: Get PLL fractional data using PLL get parameter EEMI API
Fractional data should be get using PLL get parameter EEMI API. This
stands for system-level communication (APU to PMU). Since linux
already uses a specific IOCTL function to do this and we need to
keep it that way, the pll clock ID given by linux has to be mapped
to the pll node ID that is communicated at the system-level (argument
of PLL get parameter API).
With this modification the function pm_api_clk_get_pll_frac_data is
removed from pm_api_clock.c/h because it became unused.
The clock enum is defined as 'enum clock_id'.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 20279793 | 04-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Implement PLL get mode EEMI API
This API will be used to get the currently configured PLL mode:
reset (bypassed and unlocked), integer or fractional (locked).
Signed-off-by: Mirela Simo
zynqmp: pm: Implement PLL get mode EEMI API
This API will be used to get the currently configured PLL mode:
reset (bypassed and unlocked), integer or fractional (locked).
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 5f1a5fee | 04-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Implement PLL set mode EEMI API
This API will be used to set the PLL mode: reset (unlocked), integer
or fractional (locked). If reset mode is set the PM controller will
bypass the target
zynqmp: pm: Implement PLL set mode EEMI API
This API will be used to set the PLL mode: reset (unlocked), integer
or fractional (locked). If reset mode is set the PM controller will
bypass the target PLL prior to asserting the reset. If integer or
fractional mode is set the PM controller will program and trigger
locking of the PLL. If success status is returned the PLL is locked
and its bypass is deasserted. If fractional mode is set the fractional
divider (data parameter) has to have a non-zero value prior to issuing
pll set fractional mode. The caller need to ensure that the data
parameter is properly set using pll get/set parameter EEMI API.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| d833f64c | 04-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Implement PLL get parameter EEMI API
This API will be used to get a parameter for the PLL. Parameter values
represent the values as defined in the Zynq MPSoC register reference
manual ug
zynqmp: pm: Implement PLL get parameter EEMI API
This API will be used to get a parameter for the PLL. Parameter values
represent the values as defined in the Zynq MPSoC register reference
manual ug1087.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| bfed44a1 | 02-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
zynqmp: pm: Implement PLL set parameter EEMI API
This API will be used to set a parameter for the PLL. The parameter
value that is set will have effect once the PLL mode is set to integer
or fractio
zynqmp: pm: Implement PLL set parameter EEMI API
This API will be used to set a parameter for the PLL. The parameter
value that is set will have effect once the PLL mode is set to integer
or fractional mode. Parameter values represent the values as defined
in the Zynq MPSoC register reference manual ug1087.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 8e7b27a4 | 17-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
rpi3: Remove unneeded include paths from Makefile
Change-Id: I20d164f7573ebc24935e92a924472e29c8a0e3a0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 09d40e0e | 14-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- inclu
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 07146afb | 14-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
plat/arm: Always define TSP memory region
Even though this is not used unless SPD=tspd, only defining it when
SPD_tspd is defined doesn't have any advantage and it makes it harder to
read the code.
plat/arm: Always define TSP memory region
Even though this is not used unless SPD=tspd, only defining it when
SPD_tspd is defined doesn't have any advantage and it makes it harder to
read the code.
Change-Id: I3d93135e05f39be071d16f8a47394a9a3ff54bc8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 500436b2 | 19-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
plat/arm: Remove comment that mentions LOAD_IMAGE_V2
This option was removed in v2.0.
Change-Id: I0c929fddb57d60c5eff9e45dd5ee8c636b28e6c3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
| 80c50eea | 19-Oct-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: support for native GICv2 drivers
This patch converts Tegra platforms to support native
GICv2 drivers. This involves removes Tegra's GIC driver
port platforms to use interrupt_props
Change-Id
Tegra: support for native GICv2 drivers
This patch converts Tegra platforms to support native
GICv2 drivers. This involves removes Tegra's GIC driver
port platforms to use interrupt_props
Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| ce6107c7 | 19-Oct-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: support to compile native GICv2 drivers
This patch adds a macro to allow platforms to compile native
GICv2 drivers along with Tegra handlers.
Change-Id: I8281796c09dae5704cff2daab831395d65e2
Tegra: support to compile native GICv2 drivers
This patch adds a macro to allow platforms to compile native
GICv2 drivers along with Tegra handlers.
Change-Id: I8281796c09dae5704cff2daab831395d65e261b7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| cae725bf | 18-Dec-2018 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1721 from marex/arm/master/memsize-passing-v2
plat: rcar: Move FDT from x3 to x1 |
| 85686f18 | 18-Dec-2018 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1717 from satheesbalya-arm/sb1/sb1_2629_romlib_ifc
romlib: Add platform specific jump table list |
| 8b9a0de4 | 31-Oct-2018 |
Sathees Balya <sathees.balya@arm.com> |
romlib: Add platform specific jump table list
This patch allows platforms to define their
own jump table list for library at ROM. The
file has the list of functions to be used
from library at ROM. I
romlib: Add platform specific jump table list
This patch allows platforms to define their
own jump table list for library at ROM. The
file has the list of functions to be used
from library at ROM. It can also include
other list files.
Change-Id: I721c35d7dad3dcadbb3a7f3277bfd5d3e1f6e00a
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
show more ...
|
| 06ce6912 | 13-Dec-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
plat: rcar: Move FDT from x3 to x1
As suggested, pass the FDT to BL 33 via x1 instead of x3 , to be
consistent with the other platforms.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |