Merge "fix(rcar5): prevent boot CPU hot unplug" into integration

Merge "feat(rcar): rewrite console_renesas_register() in C" into integration

feat(qemu): disable fpregs traps for QEMU in BL31

The BL31 boot process of QEMU requires, as a workaround, disabling of
fpregs trap in BL31. The fpregs trap is by default enabled and therefore
it ne

feat(qemu): disable fpregs traps for QEMU in BL31

The BL31 boot process of QEMU requires, as a workaround, disabling of
fpregs trap in BL31. The fpregs trap is by default enabled and therefore
it needed to be explicitly disabled for the BL31 setup for QEMU.

Change-Id: Id958e5e72a1fae81553ba320dcdb232bc705b835
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
f

Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
fix(fvp): increase resident text size of BL2
fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set
fix(arm): update next image's ep info with the FW config address

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feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main

feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main there are two different code paths for RESET_BL2,
one handles BL2 running in EL1 and other for BL2 running in EL3.

When RME is enabled, BL2 always runs at EL3 but the current flow calls
bl2_early_platform_setup2, bl2_plat_arch_setup instead of
bl2_el3_early_platform_setup, bl2_el3_plat_arch_setup. Adding RME,
TRANSFER_LIST, ROMLIB support in bl2_el3_* helpers makes
arm_bl2_el3_setup.c almost identical to arm_bl2_setup.c.

This patch removes bl2_el3_plat helpers and related files. Now different
combinations of RESET_TO_BL2, ENABLE_RME are handled in common bl2_setup
routines in arm_bl2_setup.c. This helps to have common place to support
new features and build flags for BL2 irrespective of which EL the BL2
runs.

BREAKING-CHANGE: This patch also changes all existing platform files and
functions that use format bl2_el3_* to bl2_plat helpers. If any platform
or out-of-tree platforms that need to support running BL2 in EL1 or EL3
must now handle it in bl2_early_platform_setup2 and bl2_plat_arch_setup.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I8d332dbe2de1db3b69319496c8d04626cdcf4140

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fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2

fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2 in EL3 case) causes increase in resident text size
of BL2.

This is applicable in case of PLAT=fvp as it includes a lot of CPU_LIBS
and might not be the case of other platforms as it includes only
specific CPU libs.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I2fd7eecebd9a2bdcbdc9fbbf4cecc2d659740931

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fix(tc): add missing platform.h include

This include is required for plat_panic_handler.

Change-Id: Ifad8ff294c396929979969a0115866030342f1f5
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-dr

fix(tc): add missing platform.h include

This include is required for plat_panic_handler.

Change-Id: Ifad8ff294c396929979969a0115866030342f1f5
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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fix(rcar5): prevent boot CPU hot unplug

The boot CPU runs both TFA and later also Trusted OS, which is
UP and can not be migrated to another CPU. Report MIGRATE_INFO_TYPE
"Uniprocessor (UP) not migr

fix(rcar5): prevent boot CPU hot unplug

The boot CPU runs both TFA and later also Trusted OS, which is
UP and can not be migrated to another CPU. Report MIGRATE_INFO_TYPE
"Uniprocessor (UP) not migrate capable 1" to the OS, so any attempts
at CPU_OFF and MIGRATE of the boot CPU would be DENIED. This has an
effect also e.g. on the Linux kernel, where it prevents stopping
boot CPU (CPU0) using CPU hotplug, which must not be allowed,
as it would interfere with the Trusted OS.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I9265115fc721e813d51f9c14e8ebe0471b12928c

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Merge "fix(mt8196): check apusys_ace_he_config address is valid" into integration

Merge changes I01e59e3a,I2fe22b37,I6b1a4aca,I10bda793,I45d2b6b2, ... into integration

* changes:
feat(stm32mp2): manage core 1 enabling
feat(st): add stm32mp_gic_cpuif_enable/disable
feat(stm3

Merge changes I01e59e3a,I2fe22b37,I6b1a4aca,I10bda793,I45d2b6b2, ... into integration

* changes:
feat(stm32mp2): manage core 1 enabling
feat(st): add stm32mp_gic_cpuif_enable/disable
feat(stm32mp2): add a ca35ss driver
feat(stm32mp2): stub PM code in serial boot
feat(st): add STM32MP_SUPPORT_PM flag
feat(st): disable FWU on serial boot devices

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fix(mt8196): check apusys_ace_he_config address is valid

The apusys_ace_he_config address is set by the image loaded by the
kernel. The address should be verified to ensure that it is valid.

Change

fix(mt8196): check apusys_ace_he_config address is valid

The apusys_ace_he_config address is set by the image loaded by the
kernel. The address should be verified to ensure that it is valid.

Change-Id: Ia811992505247944a47c7a47ae4fa0decc8f165e
Signed-off-by: Yuan-chang Hsieh <yuan-chang.hsieh@mediatek.corp-partner.google.com>

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Merge changes from topic "xlnx_misra_fixes_series1" into integration

* changes:
fix(versal2): fix misra rule 8.4 violation
fix(versal2): fix misra rule 5.7 violations
fix(versal2): fix misra r

Merge changes from topic "xlnx_misra_fixes_series1" into integration

* changes:
fix(versal2): fix misra rule 8.4 violation
fix(versal2): fix misra rule 5.7 violations
fix(versal2): fix misra rule 18.1 violations
fix(versal2): fix misra rule 10.4 violations
fix(versal2): fix misra rule 10.3 violations

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Merge changes I6deddab4,I432b05b2,I4af7371d,I2318ea4b into integration

* changes:
feat(rdv3): use SFCP PSA call instead of RSE comms
feat(tc): use SFCP PSA call instead of RSE comms
feat(tc):

Merge changes I6deddab4,I432b05b2,I4af7371d,I2318ea4b into integration

* changes:
feat(rdv3): use SFCP PSA call instead of RSE comms
feat(tc): use SFCP PSA call instead of RSE comms
feat(tc): add tc_sfcp.c
feat(sfcp): add SFCP stack and PSA call

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fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set

Enable reading HW_CONFIG device tree from transfer list entry when
RESET_BL2 is enabled.

Signed-off-by: Arunachalam Ganapathy <arunac

fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set

Enable reading HW_CONFIG device tree from transfer list entry when
RESET_BL2 is enabled.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ibcd65f3946924670ede3ba354db5bc574c70b4be

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fix(arm): update next image's ep info with the FW config address

When RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1, BL2 loads FW_CONFIG
but it fails to update the next image entry point with FW co

fix(arm): update next image's ep info with the FW config address

When RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1, BL2 loads FW_CONFIG
but it fails to update the next image entry point with FW config
address.

This fix also enables populating HW_CONFIG from platform setup routines
in BL31.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I86cc5e97cfdb0f18be647b867b1e1d82d53cdafd

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feat(rcar): rewrite console_renesas_register() in C

Replace assembler implementation of console_renesas_register() with
matching C implementation. Since it is now easily possible to pass
flags into

feat(rcar): rewrite console_renesas_register() in C

Replace assembler implementation of console_renesas_register() with
matching C implementation. Since it is now easily possible to pass
flags into console_renesas_register() and then onward to the console
initialization, adjust the signature of console_renesas_register()
and include the flags in it. Adjust both rcar_console_boot_init()
and rcar_console_runtime_init() to call console_renesas_register()
with its new combined set of parameters and drop console_set_scope()
invocation which is no longer needed, because the flags are passed
directly into console_renesas_register().

Drop console_renesas_flush() which is always a noop. Drop return
value from console_renesas_init() which is always 1.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I1c7d1a81b6922138b6e2e80f2635fcc8558685c7

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feat(stm32mp2): manage core 1 enabling

After boot, the BootROM will issue a reset of the Cortex-A35 cores.
Core 0 will boot till kernel. Core 1 is placed in WFI in TF-A BL2.
Through PSCI, Linux will

feat(stm32mp2): manage core 1 enabling

After boot, the BootROM will issue a reset of the Cortex-A35 cores.
Core 0 will boot till kernel. Core 1 is placed in WFI in TF-A BL2.
Through PSCI, Linux will ask to have Core 1 available. The PSCI platform
code is done in stm32_pwr_domain_on(). Core0 will change Core1 reset
address thanks to CA35SS_SYSCFG_VBAR_CR register to BL31 entry point.
And will reset Core1 by setting RCC_C1P1RSTCSETR_C1P1PORRST bit.
It is possible to turn core 1 on and off. But it is not possible to do
so on core 0.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I01e59e3a2398c48cc050ec4703d6610da9e9c4bd

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feat(st): add stm32mp_gic_cpuif_enable/disable

Add function to enable and disable GIC dispatcher when it is necessary
in pm functions.

Change-Id: I2fe22b3728577d3fc1292e7db7afe7183aa3fc9a
Signed-of

feat(st): add stm32mp_gic_cpuif_enable/disable

Add function to enable and disable GIC dispatcher when it is necessary
in pm functions.

Change-Id: I2fe22b3728577d3fc1292e7db7afe7183aa3fc9a
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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feat(stm32mp2): add a ca35ss driver

Move the access on the ca35ss registers in a separate file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6b1a4aca9832dfc2549f26dc85

feat(stm32mp2): add a ca35ss driver

Move the access on the ca35ss registers in a separate file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6b1a4aca9832dfc2549f26dc8579b0728db3feb5

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feat(stm32mp2): stub PM code in serial boot

When booting from USB or UART, with programmer, the low-power sequences
won't be used, some code can then be stubbed under UART and USB flags.

Change-Id:

feat(stm32mp2): stub PM code in serial boot

When booting from USB or UART, with programmer, the low-power sequences
won't be used, some code can then be stubbed under UART and USB flags.

Change-Id: I10bda7930bd809640f2b40fe46a6fa568946c09d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(st): add STM32MP_SUPPORT_PM flag

This flag will be used to enable low power features.

Change-Id: I45d2b6b2ed1da9259a654359f6e611813f92a9c9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

feat(st): disable FWU on serial boot devices

When compiling for USB or UART boot devices, it makes no sense to
enable Firmware update through PSA_FWU_SUPPORT=1.
In this case force the flag to 0, to

feat(st): disable FWU on serial boot devices

When compiling for USB or UART boot devices, it makes no sense to
enable Firmware update through PSA_FWU_SUPPORT=1.
In this case force the flag to 0, to avoid compilation issues.

Change-Id: Id7e35754fd9cf3fb3c26b8ccb947bd39c981231e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status
feat(cpufeat): advertise support for FEAT_RASv2
feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

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Merge "fix(arm): build fails on RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1" into integration

feat(rdv3): use SFCP PSA call instead of RSE comms

In a similar manner to the TC platform, add the SFCP platform
definitions for RDV3. SFCP is then used instead of RSE comms for making
PSA calls int

feat(rdv3): use SFCP PSA call instead of RSE comms

In a similar manner to the TC platform, add the SFCP platform
definitions for RDV3. SFCP is then used instead of RSE comms for making
PSA calls into the RSE.

Change-Id: I6deddab452026ba24bd2462bcf2f11846af6f80b
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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