Merge "feat(versal2): add PM support for 1-cluster 4-core topology" into integration

Merge "fix(rcar4): change the migrate information for OPTEE-OS" into integration

Merge "fix(rcar3): fix issue unable to access system RAM after warm boot" into integration

Merge "fix(tc): fix BL31 size for PLATFORM_TEST" into integration

fix(tc): fix BL31 size for PLATFORM_TEST

We need to account for the extra large BL31
when PLATFORM_TEST_TFM_TESTSUITE is enabled.

Change-Id: Ifebf839a848f3a859898f920e42e0f39cca7d2cf
Signed-off-by:

fix(tc): fix BL31 size for PLATFORM_TEST

We need to account for the extra large BL31
when PLATFORM_TEST_TFM_TESTSUITE is enabled.

Change-Id: Ifebf839a848f3a859898f920e42e0f39cca7d2cf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "imx93_minor_update" into integration

* changes:
feat(imx93): enable the s401 clock on/off handshake
fix(imx93): reduce the pmic stby off delay
feat(imx93): optimize p

Merge changes from topic "imx93_minor_update" into integration

* changes:
feat(imx93): enable the s401 clock on/off handshake
fix(imx93): reduce the pmic stby off delay
feat(imx93): optimize power switch acknowledgment timing
feat(imx93): retrieve SoC info from EdgeLock Enclave
refactor(imx93): migrate to common GICv3 driver
fix(imx93): reduce BL31 limit to reserve DRAM timing area
fix(imx93): add null terminator to mmap region array

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Merge "fix(rcar3): fix order of DRAM DT nodes for 1x4 GiB bank" into integration

Merge changes from topic "deprecate-t210-t186" into integration

* changes:
refactor(tegra): deprecate tegra186 platform
refactor(tegra): deprecate tegra210 platform

Merge "fix(versal2): correct NS entry point check for reserved regions" into integration

Merge "fix(lemans_evk): move BL2 to pIMEM instead of system IMEM" into integration

Merge changes Ic8700325,I6a3a9f28,I91a28b5f,Ia69289bf,I81d9b73a, ... into integration

* changes:
feat(cpufeat): constrain RAS_TRAP_NS_ERR_REC_ACCESS on ENABLE_FEAT_RAS
fix(build): set defaults t

Merge changes Ic8700325,I6a3a9f28,I91a28b5f,Ia69289bf,I81d9b73a, ... into integration

* changes:
feat(cpufeat): constrain RAS_TRAP_NS_ERR_REC_ACCESS on ENABLE_FEAT_RAS
fix(build): set defaults to feature flags before platform.mk
refactor(cpufeat): unify FEAT_IDTE3's definitions with arch.h
refactor(el3-runtime): generalise sysreg trapping
refactor(el3-runtime): use contexted SCR_EL3 instead of the register
build: rename default_ones to set_ones

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feat(versal2): add PM support for 1-cluster 4-core topology

Add PM node IDs for Core 2 and Core 3 of Cluster 0.

Add new pm_proc structure to support the 1 Cluster 4 cores topology and
select the pm

feat(versal2): add PM support for 1-cluster 4-core topology

Add PM node IDs for Core 2 and Core 3 of Cluster 0.

Add new pm_proc structure to support the 1 Cluster 4 cores topology and
select the pm_proc table dynamically based on topology.

Update APU_PCIL core index calculation logic to support 1-cluster
4-core topology.

Change-Id: I14ba4a2caa9a9872adaa44a78dc288ec49cbcc89
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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fix(versal2): correct NS entry point check for reserved regions

The NS entrypoint validation logic incorrectly compared the entrypoint
address against size rather than the end of the reserved region

fix(versal2): correct NS entry point check for reserved regions

The NS entrypoint validation logic incorrectly compared the entrypoint
address against size rather than the end of the reserved region
(base + size). As a result, entrypoints within reserved‑memory regions
could incorrectly pass validation.
Correct the check to treat each reserved region as [base, base + size).

Fixes: 27e722210602 ("feat(versal2): validate non-secure entry addr")
Change-Id: Ifc19f31295c6fb034862e3bca78e1d8659eb86a2
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "amd_feat_stat_tply" into integration

* changes:
fix(amd): update topology before GIC init
feat(versal2): add static topology via build arg

fix(lemans_evk): move BL2 to pIMEM instead of system IMEM

System IMEM starting range on most of Qcom platforms is reserved for
crashdump diagnostic logs. So let's rather load BL2 on pIMEM instead
to

fix(lemans_evk): move BL2 to pIMEM instead of system IMEM

System IMEM starting range on most of Qcom platforms is reserved for
crashdump diagnostic logs. So let's rather load BL2 on pIMEM instead
to allow the existing crashdump feature supported by system IMEM to
work.

XBL sets up the first window of pIMEM as 5MB starting 0x1c000000, so
it's available for TF-A (BL2, BL31) and OP-TEE stages to use.

Change-Id: I224021542c437cb645a997e7653976beff175cdc
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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Merge changes I4a94dce2,I8dccfc0c into integration

* changes:
feat: enable FEATURE_DETECTION on FVP
fix(cpufeat): fix compiler warning in feature detection

Merge "fix(juno): increase BL2 maximum size to 0x16000" into integration

Merge changes from topic "ti-am62l-clk" into integration

* changes:
feat(k3low): add board specific power management drivers and data
feat(ti): add device group filtering to clock initialization

Merge changes from topic "ti-am62l-clk" into integration

* changes:
feat(k3low): add board specific power management drivers and data
feat(ti): add device group filtering to clock initialization
feat(ti): add clock device integration to TI clock framework
feat(ti): add TI device PSC integration layer
feat(ti): add TI PSC hardware driver
feat(ti): add TI device preparation and validation driver
feat(ti): add TI core device management driver
feat(ti): add TI device power management driver
feat(ti): add TI device clock driver and power domain API
feat(ti): add TI clock management framework core
feat(ti): add TI low-frequency oscillator driver
feat(ti): add TI high-frequency oscillator driver
feat(ti): add TI 16FFT PLL driver
feat(ti): add TI generic PLL driver and control
feat(ti): add TI fixed clock driver
feat(ti): add TI clock divider driver
feat(ti): add TI clock multiplexer driver

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Merge "feat(mediatek): support write-access for DSU PMU in EL1" into integration

Merge changes from topics "xlnx_versal_ipi_build", "xlnx_versalnet_ipi_build" into integration

* changes:
feat(versal-net): add build macro support for IPI_ID_APU
feat(versal): add build macro s

Merge changes from topics "xlnx_versal_ipi_build", "xlnx_versalnet_ipi_build" into integration

* changes:
feat(versal-net): add build macro support for IPI_ID_APU
feat(versal): add build macro support for IPI_ID_APU

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fix(amd): update topology before GIC init

On platforms where the core and cluster count is determined at
runtime from the device tree, the GIC redistributor mapping uses
stale compile-time defaults.

fix(amd): update topology before GIC init

On platforms where the core and cluster count is determined at
runtime from the device tree, the GIC redistributor mapping uses
stale compile-time defaults. This causes secondary CPUs whose
affinity exceeds the default topology to be skipped during GIC
initialization, resulting in an assert during CPU bring-up.

Ensure the device tree topology is resolved before the GIC is
initialized so the redistributor mapping reflects the actual
hardware configuration.

Fixes: 8daa7377b7dc ("feat(versal2): add dynamic fetching of core and cluster")

Change-Id: Ide17dd0b3a26816c8361bc1fb4fed19aebcc6813
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(versal2): add static topology via build arg

Introduce VERSAL2_VARIANT build argument to select the CPU topology
at compile time. When VERSAL2_VARIANT=14 is passed:

- PLATFORM_CLUSTER_COUNT is

feat(versal2): add static topology via build arg

Introduce VERSAL2_VARIANT build argument to select the CPU topology
at compile time. When VERSAL2_VARIANT=14 is passed:

- PLATFORM_CLUSTER_COUNT is set to 1 and
PLATFORM_CORE_COUNT_PER_CLUSTER to 4, yielding 4 total cores.

The default configuration uses VERSAL2_VARIANT=42, providing
4 clusters with 2 cores each (8 total cores).

Platform cluster and core limits and the static power-domain tree
layout follow the selected variant.

The versal2-2vm3654 variant has a single CPU cluster of four cores
(VERSAL2_VARIANT=14) instead of the general-purpose Versal Gen 2
topology (4 clusters × 2 cores, VERSAL2_VARIANT=42).

Change-Id: Ib22c87ae58cc87da726d36a0f8370ecd97598bf5
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(k3low): add board specific power management drivers and data

Add AM62L specific clock and power domain management drivers and
data.

Change-Id: I3074801f669d24c0ab5c50f58996071ad6eed9eb
Signed-

feat(k3low): add board specific power management drivers and data

Add AM62L specific clock and power domain management drivers and
data.

Change-Id: I3074801f669d24c0ab5c50f58996071ad6eed9eb
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

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feat(ti): add TI device clock driver and power domain API

Add device clock driver and power domain API headers for TI K3 platforms.
This manages clocks attached to devices for power management opera

feat(ti): add TI device clock driver and power domain API

Add device clock driver and power domain API headers for TI K3 platforms.
This manages clocks attached to devices for power management operations.

Change-Id: I6851b9227238ff6511f4835b7e6ffd504b265ceb
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

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feat(ti): add TI clock management framework core

Add the core clock management framework for TI platforms including:
- Clock subsystem core with get/put reference counting
- Clock initialization and

feat(ti): add TI clock management framework core

Add the core clock management framework for TI platforms including:
- Clock subsystem core with get/put reference counting
- Clock initialization and state management
- Parent child clock relationship management
- Frequency setting

This provides the foundation for clock tree management.

Change-Id: I794944500097ab7b739ffb9d2748d1271be98f1d
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

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