| 9acaaded | 07-Nov-2024 |
Abhi Singh <abhi.singh@arm.com> |
fix(rpi3): expose BL1_RW to BL2 map for mboot
BL2 requires the ability to access the TCG Event Log during Measured Boot. Currently the Platform hangs since the Event Log is not exposed to BL2's mma
fix(rpi3): expose BL1_RW to BL2 map for mboot
BL2 requires the ability to access the TCG Event Log during Measured Boot. Currently the Platform hangs since the Event Log is not exposed to BL2's mmap. Define a RPI3_BL1_RW region to be added to the BL2 Image, if Measured Boot is enabled.
Change-Id: Ic236a80e73ea342b4590cfb65bafbb8ffac17085 Signed-off-by: Abhi Singh <abhi.singh@arm.com>
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| 6dfcf4e1 | 07-Nov-2024 |
Abhi Singh <abhi.singh@arm.com> |
feat(rpi3): implement eventlog handoff to BL33
At the end of BL2 measured boot, write the address and size of the TCG Event Log to NT_FW_CONFIG so that the log can be consumed later by BL33. -add dy
feat(rpi3): implement eventlog handoff to BL33
At the end of BL2 measured boot, write the address and size of the TCG Event Log to NT_FW_CONFIG so that the log can be consumed later by BL33. -add dynamic configuration helpers for the fdt -write the eventlog address and size to the fdt
Change-Id: I099dd9cc96d740ae13cb8b8e8c6b9f2e6c02accc Signed-off-by: Abhi Singh <abhi.singh@arm.com>
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| 1c800903 | 05-Nov-2024 |
Abhi Singh <abhi.singh@arm.com> |
refactor(rpi3): move mbedtls helper to common code
In order to support measured boot we need plat_get_mbedtls_heap, this function currently resides in rpi3_trusted_boot.c, but we do not need trusted
refactor(rpi3): move mbedtls helper to common code
In order to support measured boot we need plat_get_mbedtls_heap, this function currently resides in rpi3_trusted_boot.c, but we do not need trusted board boot to use measured boot, so moving this to common code removes the need to compile rpi3_trusted_boot.c
Change-Id: I6ac6dfa8c540e456d7cb6932098c921907ad086a Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Signed-off-by: Abhi Singh <abhi.singh@arm.com>
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| 682607fb | 06-Mar-2024 |
Mario Bălănică <mariobalanica02@gmail.com> |
feat(rpi5): add PCI SMCCC support
BCM2712 changes: - support all 3 PCIe RCs / segments. - don't check for link up: the RC can now be configured to fabricate all-ones AXI OKAY responses, so no mo
feat(rpi5): add PCI SMCCC support
BCM2712 changes: - support all 3 PCIe RCs / segments. - don't check for link up: the RC can now be configured to fabricate all-ones AXI OKAY responses, so no more Arm SErrors when the link is down (or other conditions).
Also, limit bus 0 to devfn 0 as accesses beyond that may result in lock-ups.
Change-Id: Ic64785cd68b22571c6638fc3f771703113bc76f6 Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
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| 6744d07d | 01-Dec-2023 |
Mario Bălănică <mariobalanica02@gmail.com> |
fix(rpi): consider MT when calculating core index from MPIDR
RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that the lowest affinity level represents a thread, but there is only o
fix(rpi): consider MT when calculating core index from MPIDR
RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that the lowest affinity level represents a thread, but there is only one thread per core.
To deal with this, simply right shift MPIDR by one affinity level to get the cluster and core IDs back into Aff1 and Aff0 as expected.
Change-Id: I2bafba38f82fd9a6ef6f2fdf2c089b754279a6de Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
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