1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 chosen { 50 /* 51 * Add some dummy entropy for Linux so it 52 * doesn't delay the boot waiting for it. 53 */ 54 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 55 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 56 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 57 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 58 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 59 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 60 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 61 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 core4 { 83 cpu = <&CPU4>; 84 }; 85 core5 { 86 cpu = <&CPU5>; 87 }; 88 core6 { 89 cpu = <&CPU6>; 90 }; 91 core7 { 92 cpu = <&CPU7>; 93 }; 94 }; 95 }; 96 97 /* 98 * The timings below are just to demonstrate working cpuidle. 99 * These values may be inaccurate. 100 */ 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 arm,psci-suspend-param = <0x0010000>; 107 local-timer-stop; 108 entry-latency-us = <300>; 109 exit-latency-us = <1200>; 110 min-residency-us = <2000>; 111 }; 112 CLUSTER_SLEEP_0: cluster-sleep-0 { 113 compatible = "arm,idle-state"; 114 arm,psci-suspend-param = <0x1010000>; 115 local-timer-stop; 116 entry-latency-us = <400>; 117 exit-latency-us = <1200>; 118 min-residency-us = <2500>; 119 }; 120 }; 121 122 amus { 123 amu: amu-0 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 mpmm_gear0: counter@0 { 128 reg = <0>; 129 enable-at-el3; 130 }; 131 132 mpmm_gear1: counter@1 { 133 reg = <1>; 134 enable-at-el3; 135 }; 136 137 mpmm_gear2: counter@2 { 138 reg = <2>; 139 enable-at-el3; 140 }; 141 }; 142 }; 143 144 CPU0:cpu@0 { 145 device_type = "cpu"; 146 compatible = "arm,armv8"; 147 reg = <0x0>; 148 enable-method = "psci"; 149 clocks = <&scmi_dvfs 0>; 150 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 151 capacity-dmips-mhz = <LIT_CAPACITY>; 152 amu = <&amu>; 153 supports-mpmm; 154 }; 155 156 CPU1:cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x100>; 160 enable-method = "psci"; 161 clocks = <&scmi_dvfs 0>; 162 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 163 capacity-dmips-mhz = <LIT_CAPACITY>; 164 amu = <&amu>; 165 supports-mpmm; 166 }; 167 168 CPU2:cpu@200 { 169 device_type = "cpu"; 170 compatible = "arm,armv8"; 171 reg = <0x200>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174 amu = <&amu>; 175 supports-mpmm; 176 }; 177 178 CPU3:cpu@300 { 179 device_type = "cpu"; 180 compatible = "arm,armv8"; 181 reg = <0x300>; 182 enable-method = "psci"; 183 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 184 amu = <&amu>; 185 supports-mpmm; 186 }; 187 188 CPU4:cpu@400 { 189 device_type = "cpu"; 190 compatible = "arm,armv8"; 191 reg = <0x400>; 192 enable-method = "psci"; 193 clocks = <&scmi_dvfs 1>; 194 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 195 capacity-dmips-mhz = <MID_CAPACITY>; 196 amu = <&amu>; 197 supports-mpmm; 198 }; 199 200 CPU5:cpu@500 { 201 device_type = "cpu"; 202 compatible = "arm,armv8"; 203 reg = <0x500>; 204 enable-method = "psci"; 205 clocks = <&scmi_dvfs 1>; 206 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 207 capacity-dmips-mhz = <MID_CAPACITY>; 208 amu = <&amu>; 209 supports-mpmm; 210 }; 211 212 CPU6:cpu@600 { 213 device_type = "cpu"; 214 compatible = "arm,armv8"; 215 reg = <0x600>; 216 enable-method = "psci"; 217 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 218 amu = <&amu>; 219 supports-mpmm; 220 }; 221 222 CPU7:cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,armv8"; 225 reg = <0x700>; 226 enable-method = "psci"; 227 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 228 amu = <&amu>; 229 supports-mpmm; 230 }; 231 }; 232 233 reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 linux,cma { 239 compatible = "shared-dma-pool"; 240 reusable; 241 size = <0x0 0x8000000>; 242 linux,cma-default; 243 }; 244 245 optee { 246 compatible = "restricted-dma-pool"; 247 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 248 }; 249 250 }; 251 252 memory { 253 device_type = "memory"; 254 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 255 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 256 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 257 }; 258 259 psci { 260 compatible = "arm,psci-1.0", "arm,psci-0.2"; 261 method = "smc"; 262 }; 263 264 cpu-pmu-little { 265 compatible = LIT_CPU_PMU_COMPATIBLE; 266 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>; 267 status = "okay"; 268 }; 269 270 cpu-pmu-mid { 271 compatible = MID_CPU_PMU_COMPATIBLE; 272 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 273 status = "okay"; 274 }; 275 276 cpu-pmu-big { 277 compatible = BIG_CPU_PMU_COMPATIBLE; 278 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 279 status = "okay"; 280 }; 281 282 sram: sram@6000000 { 283 compatible = "mmio-sram"; 284 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 285 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 289 290 cpu_scp_scmi_a2p: scp-shmem@0 { 291 compatible = "arm,scmi-shmem"; 292 reg = <0x0 0x80>; 293 }; 294 }; 295 296 mbox_db_rx: mhu@MHU_RX_ADDR { 297 compatible = MHU_RX_COMPAT; 298 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>; 299 clocks = <&soc_refclk>; 300 clock-names = "apb_pclk"; 301 #mbox-cells = <MHU_MBOX_CELLS>; 302 interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>; 303 interrupt-names = MHU_RX_INT_NAME; 304 }; 305 306 mbox_db_tx: mhu@MHU_TX_ADDR { 307 compatible = MHU_TX_COMPAT; 308 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>; 309 clocks = <&soc_refclk>; 310 clock-names = "apb_pclk"; 311 #mbox-cells = <MHU_MBOX_CELLS>; 312 interrupt-names = MHU_TX_INT_NAME; 313 }; 314 315 firmware { 316 scmi { 317 compatible = "arm,scmi"; 318 mbox-names = "tx", "rx"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 322#if TC_SCMI_PD_CTRL_EN 323 scmi_devpd: protocol@11 { 324 reg = <0x11>; 325 #power-domain-cells = <1>; 326 }; 327#endif /* TC_SCMI_PD_CTRL_EN */ 328 329 scmi_dvfs: protocol@13 { 330 reg = <0x13>; 331 #clock-cells = <1>; 332 }; 333 334 scmi_clk: protocol@14 { 335 reg = <0x14>; 336 #clock-cells = <1>; 337 }; 338 }; 339 }; 340 341 gic: interrupt-controller@GIC_CTRL_ADDR { 342 compatible = "arm,gic-v3"; 343 #address-cells = <2>; 344 #interrupt-cells = <4>; 345 #size-cells = <2>; 346 ranges; 347 interrupt-controller; 348 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 349 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 350 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>; 351 }; 352 353 timer { 354 compatible = "arm,armv8-timer"; 355 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 356 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 357 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 358 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 359 }; 360 361 spe-pmu-mid { 362 compatible = "arm,statistical-profiling-extension-v1"; 363 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 364 status = "disabled"; 365 }; 366 367 spe-pmu-big { 368 compatible = "arm,statistical-profiling-extension-v1"; 369 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 370 status = "disabled"; 371 }; 372 373 soc_refclk: refclk { 374 compatible = "fixed-clock"; 375 #clock-cells = <0>; 376 clock-frequency = <1000000000>; 377 clock-output-names = "apb_pclk"; 378 }; 379 380 soc_refclk60mhz: refclk60mhz { 381 compatible = "fixed-clock"; 382 #clock-cells = <0>; 383 clock-frequency = <60000000>; 384 clock-output-names = "iofpga_clk"; 385 }; 386 387 soc_uartclk: uartclk { 388 compatible = "fixed-clock"; 389 #clock-cells = <0>; 390 clock-frequency = <TC_UARTCLK>; 391 clock-output-names = "uartclk"; 392 }; 393 394 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 395 os_uart: serial@2a400000 { 396 compatible = "arm,pl011", "arm,primecell"; 397 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 398 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>; 399 clocks = <&soc_uartclk>, <&soc_refclk>; 400 clock-names = "uartclk", "apb_pclk"; 401 status = "okay"; 402 }; 403 404#if !TC_DPU_USE_SCMI_CLK 405 dpu_aclk: dpu_aclk { 406 compatible = "fixed-clock"; 407 #clock-cells = <0>; 408 clock-frequency = <LCD_TIMING_CLK>; 409 clock-output-names = "fpga:dpu_aclk"; 410 }; 411 412 dpu_pixel_clk: dpu-pixel-clk { 413 compatible = "fixed-clock"; 414 #clock-cells = <0>; 415 clock-frequency = <LCD_TIMING_CLK>; 416 clock-output-names = "pxclk"; 417 }; 418#endif /* !TC_DPU_USE_SCMI_CLK */ 419 420#if TC_DPU_USE_SIMPLE_PANEL 421 vpanel { 422 compatible = "panel-dpi"; 423 post-init-providers = <&pl0>; 424 port { 425 lcd_in: endpoint { 426 remote-endpoint = <&dp_pl0_out0>; 427 }; 428 }; 429 430 panel-timing { 431 LCD_TIMING; 432 }; 433 }; 434 435#else 436 vencoder { 437 compatible = "drm,virtual-encoder"; 438 port { 439 lcd_in: endpoint { 440 remote-endpoint = <&dp_pl0_out0>; 441 }; 442 }; 443 444 display-timings { 445 timing-panel { 446 LCD_TIMING; 447 }; 448 }; 449 450 }; 451#endif 452 ethernet: ethernet@ETHERNET_ADDR { 453 reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>; 454 interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>; 455 456 reg-io-width = <2>; 457 smsc,irq-push-pull; 458 }; 459 460 bp_clock24mhz: clock24mhz { 461 compatible = "fixed-clock"; 462 #clock-cells = <0>; 463 clock-frequency = <24000000>; 464 clock-output-names = "bp:clock24mhz"; 465 }; 466 467 sysreg: sysreg@SYS_REGS_ADDR { 468 compatible = "arm,vexpress-sysreg"; 469 reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 }; 473 474 fixed_3v3: v2m-3v3 { 475 compatible = "regulator-fixed"; 476 regulator-name = "3V3"; 477 regulator-min-microvolt = <3300000>; 478 regulator-max-microvolt = <3300000>; 479 regulator-always-on; 480 }; 481 482 mmci: mmci@MMC_ADDR { 483 compatible = "arm,pl180", "arm,primecell"; 484 reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>; 485 interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>, 486 <GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>; 487 wp-gpios = <&sysreg 1 0>; 488 bus-width = <4>; 489 max-frequency = <25000000>; 490 vmmc-supply = <&fixed_3v3>; 491 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 492 clock-names = "mclk", "apb_pclk"; 493 }; 494 495 gpu_clk: gpu_clk { 496 compatible = "fixed-clock"; 497 #clock-cells = <0>; 498 clock-frequency = <1000000000>; 499 }; 500 501 gpu_core_clk: gpu_core_clk { 502 compatible = "fixed-clock"; 503 #clock-cells = <0>; 504 clock-frequency = <1000000000>; 505 }; 506 507 gpu: gpu@2d000000 { 508 compatible = "arm,mali-midgard"; 509 reg = <0x0 0x2d000000 0x0 0x200000>; 510 clocks = <&gpu_core_clk>; 511 clock-names = "shadercores"; 512#if TC_SCMI_PD_CTRL_EN 513 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 514 scmi-perf-domain = <3>; 515#endif /* TC_SCMI_PD_CTRL_EN */ 516 517 pbha { 518 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 519 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 520 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 521 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 522 <22 0x32>, <24 0x22>, <28 0x32>; 523 propagate-bits = <0x0f>; 524 }; 525 }; 526 527 power_model_simple { 528 /* 529 * Numbers used are irrelevant to Titan, 530 * it helps suppressing the kernel warnings. 531 */ 532 compatible = "arm,mali-simple-power-model"; 533 static-coefficient = <2427750>; 534 dynamic-coefficient = <4687>; 535 ts = <20000 2000 (-20) 2>; 536 thermal-zone = ""; 537 }; 538 539 smmu_600: smmu@2ce00000 { 540 compatible = "arm,smmu-v3"; 541 reg = <0 0x2ce00000 0 0x20000>; 542 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>, 543 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>, 544 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>, 545 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>; 546 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 547 #iommu-cells = <1>; 548 status = "disabled"; 549 }; 550 551 smmu_700: iommu@3f000000 { 552 #iommu-cells = <1>; 553 compatible = "arm,smmu-v3"; 554 reg = <0x0 0x3f000000 0x0 0x5000000>; 555 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>, 556 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>, 557 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>; 558 interrupt-names = "eventq", "cmdq-sync", "gerror"; 559 dma-coherent; 560 status = "disabled"; 561 }; 562 563 smmu_700_dpu: iommu@4002a00000 { 564 #iommu-cells = <1>; 565 compatible = "arm,smmu-v3"; 566 reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>; 567 interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>, 568 <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>, 569 <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>; 570 interrupt-names = "eventq", "cmdq-sync", "gerror"; 571 dma-coherent; 572 status = "disabled"; 573 }; 574 575 dp0: display@DPU_ADDR { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 compatible = "arm,mali-d71"; 579 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 580 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>; 581 interrupt-names = "DPU"; 582 DPU_CLK_ATTR1; 583 584 pl0: pipeline@0 { 585 reg = <0>; 586 DPU_CLK_ATTR2; 587 pl_id = <0>; 588 ports { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 port@0 { 592 reg = <0>; 593 dp_pl0_out0: endpoint { 594 remote-endpoint = <&lcd_in>; 595 }; 596 }; 597 }; 598 }; 599 600 pl1: pipeline@1 { 601 reg = <1>; 602 DPU_CLK_ATTR3; 603 pl_id = <1>; 604 ports { 605 #address-cells = <1>; 606 #size-cells = <0>; 607 port@0 { 608 reg = <0>; 609 }; 610 }; 611 }; 612 }; 613 614 /* 615 * L3 cache in the DSU is the Memory System Component (MSC) 616 * The MPAM registers are accessed through utility bus in the DSU 617 */ 618 msc0 { 619 compatible = "arm,mpam-msc"; 620 reg = <MPAM_ADDR 0x0 0x2000>; 621 }; 622 623 ete0 { 624 compatible = "arm,embedded-trace-extension"; 625 cpu = <&CPU0>; 626 }; 627 628 ete1 { 629 compatible = "arm,embedded-trace-extension"; 630 cpu = <&CPU1>; 631 }; 632 633 ete2 { 634 compatible = "arm,embedded-trace-extension"; 635 cpu = <&CPU2>; 636 }; 637 638 ete3 { 639 compatible = "arm,embedded-trace-extension"; 640 cpu = <&CPU3>; 641 }; 642 643 ete4 { 644 compatible = "arm,embedded-trace-extension"; 645 cpu = <&CPU4>; 646 }; 647 648 ete5 { 649 compatible = "arm,embedded-trace-extension"; 650 cpu = <&CPU5>; 651 }; 652 653 ete6 { 654 compatible = "arm,embedded-trace-extension"; 655 cpu = <&CPU6>; 656 }; 657 658 ete7 { 659 compatible = "arm,embedded-trace-extension"; 660 cpu = <&CPU7>; 661 }; 662 663 trbe { 664 compatible = "arm,trace-buffer-extension"; 665 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>; 666 }; 667 668 trusty { 669 #size-cells = <0x02>; 670 #address-cells = <0x02>; 671 ranges = <0x00>; 672 compatible = "android,trusty-v1"; 673 674 virtio { 675 compatible = "android,trusty-virtio-v1"; 676 }; 677 678 test { 679 compatible = "android,trusty-test-v1"; 680 }; 681 682 log { 683 compatible = "android,trusty-log-v1"; 684 }; 685 686 irq { 687 ipi-range = <0x08 0x0f 0x08>; 688 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 689 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 690 compatible = "android,trusty-irq-v1"; 691 }; 692 }; 693 694 /* used in U-boot, Linux doesn't care */ 695 arm_ffa { 696 compatible = "arm,ffa"; 697 method = "smc"; 698 }; 699}; 700