1 /* 2 * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_SPM_DEF_H 7 #define ARM_SPM_DEF_H 8 9 #include <lib/utils_def.h> 10 #include <lib/xlat_tables/xlat_tables_defs.h> 11 12 /* 13 * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the 14 * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition 15 * at the base of DRAM. 16 */ 17 #define ARM_SP_IMAGE_BASE BL32_BASE 18 #define ARM_SP_IMAGE_LIMIT BL32_LIMIT 19 /* The maximum size of the S-EL0 payload can be 3MB */ 20 #define ARM_SP_IMAGE_SIZE ULL(0x300000) 21 22 #ifdef IMAGE_BL2 23 /* SPM Payload memory. Mapped as RW in BL2. */ 24 #define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 25 ARM_SP_IMAGE_BASE, \ 26 ARM_SP_IMAGE_SIZE, \ 27 MT_MEMORY | MT_RW | MT_SECURE) 28 #endif 29 30 #ifdef IMAGE_BL31 31 /* SPM Payload memory. Mapped as code in S-EL1 */ 32 #define ARM_SP_IMAGE_MMAP MAP_REGION2( \ 33 ARM_SP_IMAGE_BASE, \ 34 ARM_SP_IMAGE_BASE, \ 35 ARM_SP_IMAGE_SIZE, \ 36 MT_CODE | MT_SECURE | MT_USER, \ 37 PAGE_SIZE) 38 #endif 39 40 /* 41 * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into 42 * S-EL0, so it is mapped with RW permission from EL3 and with RO permission 43 * from S-EL0. Placed after SPM Payload memory. 44 */ 45 #define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE) 46 #define PLAT_SPM_BUF_SIZE ULL(0x100000) 47 48 #define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \ 49 PLAT_SPM_BUF_BASE, \ 50 PLAT_SPM_BUF_SIZE, \ 51 MT_RW_DATA | MT_SECURE) 52 #define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \ 53 PLAT_SPM_BUF_BASE, \ 54 PLAT_SPM_BUF_BASE, \ 55 PLAT_SPM_BUF_SIZE, \ 56 MT_RO_DATA | MT_SECURE | MT_USER,\ 57 PAGE_SIZE) 58 59 /* 60 * Memory shared between Normal world and Secure world. 61 * In this area, PLAT_SP_IMAGE_NS_BUF and etc memories are located. 62 */ 63 #define ARM_SPM_NS_MEM_BASE (ARM_AP_TZC_DRAM1_BASE - \ 64 ARM_SPM_NS_MEM_SIZE) 65 #define ARM_SPM_NS_MEM_SIZE ULL(0x100000) 66 67 /* 68 * Memory shared between Normal world and S-EL0 for passing data during service 69 * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and 70 * S-EL0. 71 */ 72 #define PLAT_SP_IMAGE_NS_BUF_BASE (ARM_SPM_NS_MEM_BASE) 73 #define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) 74 #define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 75 PLAT_SP_IMAGE_NS_BUF_BASE, \ 76 PLAT_SP_IMAGE_NS_BUF_BASE, \ 77 PLAT_SP_IMAGE_NS_BUF_SIZE, \ 78 MT_RW_DATA | MT_NS | MT_USER, \ 79 PAGE_SIZE) 80 81 /* 82 * RW memory, which uses the remaining Trusted DRAM. Placed after the memory 83 * shared between Secure and Non-secure worlds, or after the platform specific 84 * buffers, if defined. First there is the stack memory for all CPUs and then 85 * there is the common heap memory. Both are mapped with RW permissions. 86 */ 87 #define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE 88 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000) 89 #define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 90 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 91 92 #define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 93 ARM_SP_IMAGE_STACK_TOTAL_SIZE) 94 #define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - \ 95 PLAT_SP_PSEUDO_S_CRB_SIZE - \ 96 ARM_SP_IMAGE_HEAP_BASE) 97 98 #define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \ 99 PLAT_SP_IMAGE_STACK_BASE, \ 100 PLAT_SP_IMAGE_STACK_BASE, \ 101 (ARM_SP_IMAGE_LIMIT - \ 102 PLAT_SP_PSEUDO_S_CRB_SIZE - \ 103 PLAT_SP_IMAGE_STACK_BASE), \ 104 MT_RW_DATA | MT_SECURE | MT_USER,\ 105 PAGE_SIZE) 106 107 #define PLAT_SP_PSEUDO_NS_CRB_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 108 PLAT_SP_IMAGE_NS_BUF_SIZE) 109 #define PLAT_SP_PSEUDO_NS_CRB_SIZE SZ_16K 110 #define ARM_SP_PSEUDO_NS_CRB_MMAP MAP_REGION_FLAT( \ 111 PLAT_SP_PSEUDO_NS_CRB_BASE,\ 112 PLAT_SP_PSEUDO_NS_CRB_SIZE,\ 113 MT_DEVICE | MT_RW | \ 114 MT_NS | MT_USER) 115 116 #define PLAT_SP_PSEUDO_S_CRB_BASE (ARM_SP_IMAGE_HEAP_BASE + \ 117 ARM_SP_IMAGE_HEAP_SIZE) 118 #define PLAT_SP_PSEUDO_S_CRB_SIZE SZ_4K 119 #define ARM_SP_PSEUDO_S_CRB_MMAP MAP_REGION_FLAT( \ 120 PLAT_SP_PSEUDO_S_CRB_BASE,\ 121 PLAT_SP_PSEUDO_S_CRB_SIZE,\ 122 MT_DEVICE | MT_RW | \ 123 MT_SECURE | MT_USER) 124 125 126 /* Total number of memory regions with distinct properties */ 127 #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 128 129 /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ 130 #define PLAT_SPM_COOKIE_0 ULL(0) 131 #define PLAT_SPM_COOKIE_1 ULL(0) 132 133 #endif /* ARM_SPM_DEF_H */ 134