1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <aem_generic.h> 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10 11cpu_reset_prologue aem_generic 12 13func aem_generic_core_pwr_dwn 14 /* --------------------------------------------- 15 * AEM model supports L3 caches in which case L2 16 * will be private per core caches and flush 17 * from L1 to L2 is not sufficient. 18 * --------------------------------------------- 19 */ 20 mrs x1, clidr_el1 21 22 /* --------------------------------------------- 23 * Check if L3 cache is implemented. 24 * --------------------------------------------- 25 */ 26 tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 27 28 /* --------------------------------------------- 29 * There is no L3 cache, flush L1 to L2 only. 30 * --------------------------------------------- 31 */ 32 mov x0, #DCCISW 33 b.eq dcsw_op_level1 34 35 mov x18, x30 36 37 /* --------------------------------------------- 38 * Flush L1 cache to L2. 39 * --------------------------------------------- 40 */ 41 bl dcsw_op_level1 42 mov x30, x18 43 44 /* --------------------------------------------- 45 * Flush L2 cache to L3. 46 * --------------------------------------------- 47 */ 48 mov x0, #DCCISW 49 b dcsw_op_level2 50endfunc aem_generic_core_pwr_dwn 51 52func aem_generic_cluster_pwr_dwn 53 /* --------------------------------------------- 54 * Flush all caches to PoC. 55 * --------------------------------------------- 56 */ 57 mov x0, #DCCISW 58 b dcsw_op_all 59endfunc aem_generic_cluster_pwr_dwn 60 61cpu_reset_func_start aem_generic 62cpu_reset_func_end aem_generic 63 64 /* --------------------------------------------- 65 * This function provides cpu specific 66 * register information for crash reporting. 67 * It needs to return with x6 pointing to 68 * a list of register names in ascii and 69 * x8 - x15 having values of registers to be 70 * reported. 71 * --------------------------------------------- 72 */ 73.section .rodata.aem_generic_regs, "aS" 74aem_generic_regs: /* The ascii list of register names to be reported */ 75 .asciz "" /* no registers to report */ 76 77func aem_generic_cpu_reg_dump 78 adr x6, aem_generic_regs 79 ret 80endfunc aem_generic_cpu_reg_dump 81 82 83/* cpu_ops for Base AEM FVP */ 84declare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \ 85 aem_generic_core_pwr_dwn, \ 86 aem_generic_cluster_pwr_dwn 87 88/* cpu_ops for Foundation FVP */ 89declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, aem_generic_reset_func, \ 90 aem_generic_core_pwr_dwn, \ 91 aem_generic_cluster_pwr_dwn 92