1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * GPIO related constants 29 ******************************************************************************/ 30 #define GPIO_BASE (IO_PHYS + 0x00005000) 31 #define IOCFG_LM_BASE (IO_PHYS + 0x01B50000) 32 #define IOCFG_RB0_BASE (IO_PHYS + 0x01C50000) 33 #define IOCFG_RB1_BASE (IO_PHYS + 0x01C60000) 34 #define IOCFG_BM0_BASE (IO_PHYS + 0x01D20000) 35 #define IOCFG_BM1_BASE (IO_PHYS + 0x01D30000) 36 #define IOCFG_BM2_BASE (IO_PHYS + 0x01D40000) 37 #define IOCFG_LT0_BASE (IO_PHYS + 0x01E20000) 38 #define IOCFG_LT1_BASE (IO_PHYS + 0x01E30000) 39 #define IOCFG_RT_BASE (IO_PHYS + 0x01F20000) 40 41 /******************************************************************************* 42 * SPM related constants 43 ******************************************************************************/ 44 #define SPM_BASE (IO_PHYS + 0x0C001000) 45 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 46 #define CKSYS_BASE (IO_PHYS) 47 48 /******************************************************************************* 49 * dvfsrc related constants 50 ******************************************************************************/ 51 #define DVFSRC_BASE (IO_PHYS + 0x0C00F000) 52 53 #define MTK_LPM_SRAM_BASE (0x11B000) 54 55 /******************************************************************************* 56 * mfgsys related constants 57 ******************************************************************************/ 58 #define MFGSYS_BASE (IO_PHYS + 0x03000000) 59 60 /******************************************************************************* 61 * PERI related constants 62 ******************************************************************************/ 63 #define PERICFG_AO_BASE (IO_PHYS + 0x01036000) 64 #define PERICFG_AO_SIZE (0x1000) 65 66 /******************************************************************************* 67 * APMIX related constants 68 ******************************************************************************/ 69 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 70 #define APMIXEDSYS_REG_SIZE 0x1000 71 72 /******************************************************************************* 73 * UART related constants 74 ******************************************************************************/ 75 #define UART0_BASE (IO_PHYS + 0x01002000) 76 #define UART_BAUDRATE (115200) 77 78 /******************************************************************************* 79 * SSPM CFGREG related constants 80 ******************************************************************************/ 81 #define SSPM_REG_OFFSET (0x40000) 82 #define SSPM_CFGREG_BASE (IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET) 83 #define SSPM_CFGREG_SIZE (0x1000) 84 85 /******************************************************************************* 86 * SSPM_MBOX_3 related constants 87 ******************************************************************************/ 88 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x0C380000) 89 #define SSPM_MBOX_3_SIZE (0x1000) 90 91 /******************************************************************************* 92 * LPM syssram related constants 93 ******************************************************************************/ 94 #define MTK_LPM_SRAM_BASE (0x11B000) 95 #define MTK_LPM_SRAM_MAP_SIZE (0x1000) 96 97 /******************************************************************************* 98 * Infra IOMMU related constants 99 ******************************************************************************/ 100 #define PERICFG_AO_BASE (IO_PHYS + 0x01036000) 101 #define PERICFG_AO_REG_SIZE (0x1000) 102 103 /******************************************************************************* 104 * CIRQ related constants 105 ******************************************************************************/ 106 #define SYS_CIRQ_BASE (IO_PHYS + 204000) 107 #define MD_WDT_IRQ_BIT_ID (519) 108 #define CIRQ_REG_NUM (19) 109 #define CIRQ_SPI_START (128) 110 #define CIRQ_IRQ_NUM (598) 111 112 /******************************************************************************* 113 * MM IOMMU & SMI related constants 114 ******************************************************************************/ 115 #define SMI_LARB_0_BASE (IO_PHYS + 0x0401c000) 116 #define SMI_LARB_1_BASE (IO_PHYS + 0x0401d000) 117 #define SMI_LARB_2_BASE (IO_PHYS + 0x0f002000) 118 #define SMI_LARB_4_BASE (IO_PHYS + 0x0602e000) 119 #define SMI_LARB_7_BASE (IO_PHYS + 0x07010000) 120 #define SMI_LARB_9_BASE (IO_PHYS + 0x0502e000) 121 #define SMI_LARB_11_BASE (IO_PHYS + 0x0582e000) 122 #define SMI_LARB_13_BASE (IO_PHYS + 0x0a001000) 123 #define SMI_LARB_14_BASE (IO_PHYS + 0x0a002000) 124 #define SMI_LARB_16_BASE (IO_PHYS + 0x0a00f000) 125 #define SMI_LARB_17_BASE (IO_PHYS + 0x0a010000) 126 #define SMI_LARB_19_BASE (IO_PHYS + 0x0b10f000) 127 #define SMI_LARB_20_BASE (IO_PHYS + 0x0b00f000) 128 #define SMI_LARB_REG_RNG_SIZE (0x1000) 129 #define MMSYS_CONFIG_BASE (IO_PHYS + 0x04000000) 130 #define DISP_MUTEX_BASE (IO_PHYS + 0x04001000) 131 #define DISP_OVL0_BASE (IO_PHYS + 0x04002000) 132 #define DISP_OVL1_BASE (IO_PHYS + 0x04003000) 133 #define DISP_RDMA0_BASE (IO_PHYS + 0x04006000) 134 #define DISP_COLOR0_BASE (IO_PHYS + 0x04008000) 135 #define DISP_CCORR0_BASE (IO_PHYS + 0x0400A000) 136 #define DISP_CCORR2_BASE (IO_PHYS + 0x0400C000) 137 #define DISP_AAL0_BASE (IO_PHYS + 0x0400E000) 138 #define DISP_GAMMA0_BASE (IO_PHYS + 0x04010000) 139 #define DISP_DITHER0_BASE (IO_PHYS + 0x04012000) 140 #define MM_IOMMU_BASE (IO_PHYS + 0x0e802000 + 0x4000) 141 #define APU_IOMMU_BASE (IO_PHYS + 0x09010000) 142 143 #define IOMMU_REG_RNG_SIZE (0x5000) 144 145 /******************************************************************************* 146 * System counter frequency related constants 147 ******************************************************************************/ 148 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 149 #define SYS_COUNTER_FREQ_IN_MHZ (13) 150 151 /******************************************************************************* 152 * Platform binary types for linking 153 ******************************************************************************/ 154 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 155 #define PLATFORM_LINKER_ARCH aarch64 156 157 /******************************************************************************* 158 * Generic platform constants 159 ******************************************************************************/ 160 #define PLATFORM_STACK_SIZE (0x800) 161 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 162 #define SOC_CHIP_ID U(0x8189) 163 164 /******************************************************************************* 165 * Platform memory map related constants 166 ******************************************************************************/ 167 #define TZRAM_BASE (0x54600000) 168 #define TZRAM_SIZE (0x00200000) 169 170 /******************************************************************************* 171 * BL31 specific defines. 172 ******************************************************************************/ 173 /* 174 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 175 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 176 * little space for growth. 177 */ 178 #define BL31_BASE (TZRAM_BASE + 0x1000) 179 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 180 181 /******************************************************************************* 182 * GIC-600 & interrupt handling related constants 183 ******************************************************************************/ 184 /* Base MTK_platform compatible GIC memory map */ 185 #define BASE_GICD_BASE (MT_GIC_BASE) 186 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 187 #define DEV_IRQ_ID 300 188 189 #define PLAT_MTK_G1S_IRQ_PROPS(grp) \ 190 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \ 191 GIC_INTR_CFG_LEVEL) 192 193 /******************************************************************************* 194 * Platform specific page table and MMU setup constants 195 ******************************************************************************/ 196 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 197 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 198 #define MAX_XLAT_TABLES (16) 199 #define MAX_MMAP_REGIONS (16) 200 201 /******************************************************************************* 202 * SYSTIMER related definitions 203 ******************************************************************************/ 204 #define SYSTIMER_BASE (IO_PHYS + 0x0CC10000) 205 206 /******************************************************************************* 207 * SPMI related definitions 208 ******************************************************************************/ 209 #define SPMI_MST_P_BASE (IO_PHYS + 0x0CC00000) 210 #define PMIF_SPMI_P_BASE (IO_PHYS + 0x0CC06000) 211 #define SPMI_MST_P_SIZE (0x1000) 212 213 /******************************************************************************* 214 * PWRAP related definitions 215 ******************************************************************************/ 216 #define PMICSPI_MST_BASE (IO_PHYS + 0x0c013000) 217 #define PMICSPI_MST_SIZE (0x1000) 218 #define PMIC_WRAP_BASE (IO_PHYS + 0x0CC04000) 219 #define PMIF_SPI_BASE (0x1CC04000) 220 #define PWRAP_REG_BASE (0x1C013000) 221 #define PWRAP_WRAP_EN (PWRAP_REG_BASE + 0x14) 222 223 /******************************************************************************* 224 * PMIC regsister related definitions 225 ******************************************************************************/ 226 #define PMIC_REG_BASE (0x0000) 227 #define PWRAP_SIZE (0x1000) 228 #define DEW_READ_TEST (PMIC_REG_BASE + 0x040e) 229 #define DEW_WRITE_TEST (PMIC_REG_BASE + 0x0410) 230 231 /******************************************************************************* 232 * Differentiate between 3G and 2.6G-related definitions 233 ******************************************************************************/ 234 #define EFUSEC_BASE (IO_PHYS + 0x01F10000) 235 #define CHIP_ID_REG (EFUSEC_BASE + 0x7A0) 236 #define CPU_SEG_ID_REG (EFUSEC_BASE + 0x7E0) 237 238 #define MTK_CPU_ID_MT8189 0x81890000 239 #define MTK_CPU_SEG_ID_MT8189G 0x20 240 #define MTK_CPU_SEG_ID_MT8189H 0x21 241 242 /******************************************************************************* 243 * Thermal related constants 244 ******************************************************************************/ 245 #define INFRACFG_BASE (IO_PHYS + 0x0020E000) 246 #define THERM_CTRL_AP_BASE (IO_PHYS + 0x00315000) 247 #define THERM_AP_REG_SIZE (0x1000) 248 #define THERM_CTRL_MCU_BASE (IO_PHYS + 0x00316000) 249 #define THERM_MCU_REG_SIZE (0x1000) 250 251 #define THERMAL_CSRAM_BASE (0x00102500) 252 #define THERMAL_CSRAM_SIZE (0x400) 253 254 /******************************************************************************* 255 * CPU PM definitions 256 ******************************************************************************/ 257 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 258 #define PLAT_CPU_PM_ILDO_ID (6) 259 #define CPU_IDLE_SRAM_BASE (0x11B000) 260 #define CPU_IDLE_SRAM_SIZE (0x1000) 261 262 /******************************************************************************* 263 * SPM related constants 264 ******************************************************************************/ 265 #define SPM_BASE (IO_PHYS + 0x0C001000) 266 #define SPM_REG_SIZE (0x1000) 267 268 /******************************************************************************* 269 * CPU_EB related constants 270 ******************************************************************************/ 271 #define CPU_EB_TCM_BASE (0x0C56F000) 272 #define CPU_EB_TCM_SIZE (0x1000) 273 #define CPU_EB_MBOX3_OFFSET (0xCE0) 274 275 #endif /* PLATFORM_DEF_H */ 276