1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27ifeq (${ENABLE_RME},1) 28FVP_TRUSTED_SRAM_SIZE := 384 29else 30FVP_TRUSTED_SRAM_SIZE := 256 31endif 32 33# Macro to enable helpers for running SPM tests. Disabled by default. 34PLAT_TEST_SPM := 0 35 36 37# Enable passing the DT to BL33 in x0 by default. 38USE_KERNEL_DT_CONVENTION := 1 39 40# By default dont build CPUs with no FVP model. 41BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 42 43ENABLE_FEAT_AMU := 2 44ENABLE_FEAT_AMUv1p1 := 2 45ENABLE_FEAT_HCX := 2 46ENABLE_FEAT_RNG := 2 47ENABLE_FEAT_TWED := 2 48ENABLE_FEAT_GCS := 2 49 50ifeq (${ARCH}, aarch64) 51 52ifeq (${SPM_MM}, 0) 53ifeq (${CTX_INCLUDE_FPREGS}, 0) 54 ENABLE_SME_FOR_NS := 2 55 ENABLE_SME2_FOR_NS := 2 56else 57 ENABLE_SVE_FOR_NS := 0 58 ENABLE_SME_FOR_NS := 0 59 ENABLE_SME2_FOR_NS := 0 60endif 61endif 62 63 ENABLE_BRBE_FOR_NS := 2 64 ENABLE_TRBE_FOR_NS := 2 65 ENABLE_FEAT_D128 := 2 66 ENABLE_FEAT_FPMR := 2 67 ENABLE_FEAT_MOPS := 2 68 ENABLE_FEAT_FGWTE3 := 2 69 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 70endif 71 72ENABLE_SYS_REG_TRACE_FOR_NS := 2 73ENABLE_FEAT_CSV2_2 := 2 74ENABLE_FEAT_CSV2_3 := 2 75ENABLE_FEAT_DEBUGV8P9 := 2 76ENABLE_FEAT_DIT := 2 77ENABLE_FEAT_PAN := 2 78ENABLE_FEAT_VHE := 2 79CTX_INCLUDE_NEVE_REGS := 2 80ENABLE_FEAT_SEL2 := 2 81ENABLE_TRF_FOR_NS := 2 82ENABLE_FEAT_ECV := 2 83ENABLE_FEAT_FGT := 2 84ENABLE_FEAT_FGT2 := 2 85ENABLE_FEAT_THE := 2 86ENABLE_FEAT_TCR2 := 2 87ENABLE_FEAT_S2PIE := 2 88ENABLE_FEAT_S1PIE := 2 89ENABLE_FEAT_S2POE := 2 90ENABLE_FEAT_S1POE := 2 91ENABLE_FEAT_SCTLR2 := 2 92ENABLE_FEAT_MTE2 := 2 93ENABLE_FEAT_LS64_ACCDATA := 2 94 95ifeq (${ENABLE_RME},1) 96 ENABLE_FEAT_MEC := 2 97 RMMD_ENABLE_IDE_KEY_PROG := 1 98endif 99 100# The FVP platform depends on this macro to build with correct GIC driver. 101$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 102 103# Pass FVP_CLUSTER_COUNT to the build system. 104$(eval $(call add_define,FVP_CLUSTER_COUNT)) 105 106# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 107$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 108 109# Pass FVP_MAX_PE_PER_CPU to the build system. 110$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 111 112# Pass FVP_GICR_REGION_PROTECTION to the build system. 113$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 114 115# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 116$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 117 118# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 119# choose the CCI driver , else the CCN driver 120ifeq ($(FVP_CLUSTER_COUNT), 0) 121$(error "Incorrect cluster count specified for FVP port") 122else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 123FVP_INTERCONNECT_DRIVER := FVP_CCI 124else 125FVP_INTERCONNECT_DRIVER := FVP_CCN 126endif 127 128$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 129 130# Choose the GIC sources depending upon the how the FVP will be invoked 131ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 132USE_GIC_DRIVER := 3 133 134# The GIC model (GIC-600 or GIC-500) will be detected at runtime 135GICV3_SUPPORT_GIC600 := 1 136GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 137 138FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 139ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 140BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 141endif 142 143ifeq (${HW_ASSISTED_COHERENCY}, 0) 144FVP_DT_PREFIX := fvp-base-gicv3-psci 145else 146FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 147endif 148else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 149USE_GIC_DRIVER := 5 150ENABLE_FEAT_GCIE := 1 151BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 152FVP_DT_PREFIX := fvp-base-gicv5-psci 153ifneq ($(SPD),none) 154 $(error Error: GICv5 is not compatible with SPDs) 155endif 156ifeq ($(ENABLE_RME),1) 157 $(error Error: GICv5 is not compatible with RME) 158endif 159else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 160USE_GIC_DRIVER := 2 161 162# No GICv4 extension 163GIC_ENABLE_V4_EXTN := 0 164$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 165 166FVP_DT_PREFIX := fvp-base-gicv2-psci 167else 168$(error "Incorrect GIC driver chosen on FVP port") 169endif 170 171ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 172FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 173else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 174FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 175 plat/arm/common/arm_ccn.c 176else 177$(error "Incorrect CCN driver chosen on FVP port") 178endif 179 180FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 181 plat/arm/board/fvp/fvp_security.c \ 182 plat/arm/common/arm_tzc400.c 183 184 185PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 186 -Iinclude/lib/psa 187 188 189PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 190 191FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 192 193ifeq (${ARCH}, aarch64) 194 195# select a different set of CPU files, depending on whether we compile for 196# hardware assisted coherency cores or not 197ifeq (${HW_ASSISTED_COHERENCY}, 0) 198# Cores used without DSU 199 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 200 lib/cpus/aarch64/cortex_a53.S \ 201 lib/cpus/aarch64/cortex_a57.S \ 202 lib/cpus/aarch64/cortex_a72.S \ 203 lib/cpus/aarch64/cortex_a73.S 204else 205# Cores used with DSU only 206 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 207 # AArch64-only cores 208 # TODO: add all cores to the appropriate lists 209 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 210 lib/cpus/aarch64/cortex_a65ae.S \ 211 lib/cpus/aarch64/cortex_a76.S \ 212 lib/cpus/aarch64/cortex_a76ae.S \ 213 lib/cpus/aarch64/cortex_a77.S \ 214 lib/cpus/aarch64/cortex_a78.S \ 215 lib/cpus/aarch64/cortex_a78_ae.S \ 216 lib/cpus/aarch64/cortex_a78c.S \ 217 lib/cpus/aarch64/cortex_a710.S \ 218 lib/cpus/aarch64/cortex_a715.S \ 219 lib/cpus/aarch64/cortex_a720.S \ 220 lib/cpus/aarch64/cortex_a720_ae.S \ 221 lib/cpus/aarch64/neoverse_n1.S \ 222 lib/cpus/aarch64/neoverse_n2.S \ 223 lib/cpus/aarch64/neoverse_v1.S \ 224 lib/cpus/aarch64/neoverse_e1.S \ 225 lib/cpus/aarch64/cortex_x2.S \ 226 lib/cpus/aarch64/cortex_x4.S 227 endif 228 # AArch64/AArch32 cores 229 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 230 lib/cpus/aarch64/cortex_a75.S 231endif 232 233#Include all CPUs to build to support all-errata build. 234ifeq (${ENABLE_ERRATA_ALL},1) 235 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 236 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 237 lib/cpus/aarch64/cortex_a510.S \ 238 lib/cpus/aarch64/cortex_a520.S \ 239 lib/cpus/aarch64/cortex_a725.S \ 240 lib/cpus/aarch64/cortex_x1.S \ 241 lib/cpus/aarch64/cortex_x3.S \ 242 lib/cpus/aarch64/cortex_x925.S \ 243 lib/cpus/aarch64/neoverse_n3.S \ 244 lib/cpus/aarch64/neoverse_v2.S \ 245 lib/cpus/aarch64/neoverse_v3.S 246endif 247 248#Build AArch64-only CPUs with no FVP model yet. 249ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 250 # travis/gelas need these 251 ERRATA_SME_POWER_DOWN := 1 252 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \ 253 lib/cpus/aarch64/nevis.S \ 254 lib/cpus/aarch64/travis.S \ 255 lib/cpus/aarch64/cortex_alto.S \ 256 lib/cpus/aarch64/canyon.S 257endif 258 259else 260FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 261 lib/cpus/aarch32/cortex_a57.S \ 262 lib/cpus/aarch32/cortex_a53.S 263endif 264 265BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 266 drivers/arm/sp805/sp805.c \ 267 drivers/delay_timer/delay_timer.c \ 268 drivers/io/io_semihosting.c \ 269 lib/semihosting/semihosting.c \ 270 lib/semihosting/${ARCH}/semihosting_call.S \ 271 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 272 plat/arm/board/fvp/fvp_bl1_setup.c \ 273 plat/arm/board/fvp/fvp_cpu_pwr.c \ 274 plat/arm/board/fvp/fvp_err.c \ 275 plat/arm/board/fvp/fvp_io_storage.c \ 276 plat/arm/board/fvp/fvp_topology.c \ 277 ${FVP_CPU_LIBS} \ 278 ${FVP_INTERCONNECT_SOURCES} 279 280ifeq (${USE_SP804_TIMER},1) 281BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 282else 283BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 284endif 285 286 287BL2_SOURCES += drivers/arm/sp805/sp805.c \ 288 drivers/io/io_semihosting.c \ 289 lib/utils/mem_region.c \ 290 lib/semihosting/semihosting.c \ 291 lib/semihosting/${ARCH}/semihosting_call.S \ 292 plat/arm/board/fvp/fvp_bl2_setup.c \ 293 plat/arm/board/fvp/fvp_err.c \ 294 plat/arm/board/fvp/fvp_io_storage.c \ 295 plat/arm/common/arm_nor_psci_mem_protect.c \ 296 ${FVP_SECURITY_SOURCES} 297 298 299ifeq (${COT_DESC_IN_DTB},1) 300BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 301endif 302 303ifeq (${ENABLE_RME},1) 304BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 305 plat/arm/board/fvp/fvp_cpu_pwr.c 306 307BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 308 plat/arm/board/fvp/fvp_realm_attest_key.c \ 309 plat/arm/board/fvp/fvp_el3_token_sign.c \ 310 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 311 plat/arm/common/plat_rmm_mem_carveout.c 312endif 313 314ifneq (${ENABLE_FEAT_RNG_TRAP},0) 315BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 316endif 317 318ifeq (${RESET_TO_BL2},1) 319BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 320 plat/arm/board/fvp/fvp_cpu_pwr.c \ 321 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 322 ${FVP_CPU_LIBS} \ 323 ${FVP_INTERCONNECT_SOURCES} 324endif 325 326ifeq (${USE_SP804_TIMER},1) 327BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 328endif 329 330BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 331 ${FVP_SECURITY_SOURCES} 332 333ifeq (${USE_SP804_TIMER},1) 334BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 335endif 336 337BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 338 drivers/arm/smmu/smmu_v3.c \ 339 drivers/delay_timer/delay_timer.c \ 340 drivers/cfi/v2m/v2m_flash.c \ 341 lib/utils/mem_region.c \ 342 plat/arm/board/fvp/fvp_bl31_setup.c \ 343 plat/arm/board/fvp/fvp_console.c \ 344 plat/arm/board/fvp/fvp_pm.c \ 345 plat/arm/board/fvp/fvp_topology.c \ 346 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 347 plat/arm/board/fvp/fvp_cpu_pwr.c \ 348 plat/arm/common/arm_nor_psci_mem_protect.c \ 349 ${FVP_CPU_LIBS} \ 350 ${FVP_INTERCONNECT_SOURCES} \ 351 ${FVP_SECURITY_SOURCES} 352 353# Support for fconf in BL31 354# Added separately from the above list for better readability 355ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 356BL31_SOURCES += lib/fconf/fconf.c \ 357 lib/fconf/fconf_dyn_cfg_getter.c \ 358 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 359 360BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 361 362ifeq (${SEC_INT_DESC_IN_FCONF},1) 363BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 364endif 365 366endif 367 368ifeq (${USE_SP804_TIMER},1) 369BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 370else 371BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 372endif 373 374# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 375FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 376 377FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 378$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 379HW_CONFIG := ${FVP_HW_CONFIG} 380 381HW_CONFIG_BASE ?= 0x82000000 382 383# Set default initrd base 128MiB offset of the default kernel address in FVP 384INITRD_BASE ?= 0x90000000 385 386# Kernel base address supports Linux kernels before v5.7 387# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 388ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 389 PRELOADED_BL33_BASE ?= 0x80080000 390 ifeq (${RESET_TO_BL31},1) 391 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 392 endif 393endif 394 395ifeq (${TRANSFER_LIST}, 0) 396FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 397 ${PLAT}_fw_config.dts \ 398 ${PLAT}_tb_fw_config.dts \ 399 ${PLAT}_soc_fw_config.dts \ 400 ${PLAT}_nt_fw_config.dts \ 401 ) 402 403FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 404FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 405FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 406FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 407 408ifeq (${SPD},tspd) 409FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 410FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 411 412# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 413$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 414endif 415 416# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 417$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 418# Add the NT_FW_CONFIG to FIP and specify the same to certtool 419$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 420endif 421 422ifeq (${SPD},spmd) 423 424ifeq ($(ARM_SPMC_MANIFEST_DTS),) 425ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 426endif 427 428FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 429FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 430 431# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 432$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 433endif 434 435# Add the HW_CONFIG to FIP and specify the same to certtool 436$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 437 438ifeq (${TRANSFER_LIST}, 1) 439 440ifeq ($(RESET_TO_BL31), 1) 441FW_HANDOFF_SIZE := 20000 442 443TRANSFER_LIST_DTB_OFFSET := 0x20 444$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 445endif 446endif 447 448ifeq (${HOB_LIST}, 1) 449include lib/hob/hob.mk 450endif 451 452# Enable dynamic mitigation support by default 453DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 454 455ifneq (${ENABLE_FEAT_AMU},0) 456BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 457 lib/cpus/aarch64/cpuamu_helpers.S 458 459ifeq (${HW_ASSISTED_COHERENCY}, 1) 460BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 461 lib/cpus/aarch64/neoverse_n1_pubsub.c 462endif 463endif 464 465ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 466 ifeq (${ENABLE_FEAT_RAS},1) 467 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 468 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 469 else 470 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 471 endif 472 else 473 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 474 endif 475endif 476 477ifneq (${ENABLE_STACK_PROTECTOR},0) 478PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 479endif 480 481# Enable the dynamic translation tables library. 482ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 483 ifeq (${ARCH},aarch32) 484 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 485 else # AArch64 486 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 487 endif 488endif 489 490ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 491 ifeq (${ARCH},aarch32) 492 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 493 else # AArch64 494 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 495 ifeq (${SPD},tspd) 496 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 497 endif 498 endif 499endif 500 501ifeq (${USE_DEBUGFS},1) 502 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 503endif 504 505# Add support for platform supplied linker script for BL31 build 506$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 507 508ifneq (${RESET_TO_BL2}, 0) 509 override BL1_SOURCES = 510endif 511 512include plat/arm/board/common/board_common.mk 513include plat/arm/common/arm_common.mk 514 515ifeq (${MEASURED_BOOT},1) 516BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 517 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 518 lib/psa/measured_boot.c 519 520BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 521 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 522 lib/psa/measured_boot.c 523endif 524 525ifeq (${DRTM_SUPPORT}, 1) 526BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 527 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 528 plat/arm/board/fvp/fvp_drtm_err.c \ 529 plat/arm/board/fvp/fvp_drtm_measurement.c \ 530 plat/arm/board/fvp/fvp_drtm_stub.c \ 531 plat/arm/common/arm_dyn_cfg.c \ 532 plat/arm/board/fvp/fvp_err.c 533endif 534 535ifeq (${TRUSTED_BOARD_BOOT}, 1) 536BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 537BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 538 539# FVP being a development platform, enable capability to disable Authentication 540# dynamically if TRUSTED_BOARD_BOOT is set. 541DYN_DISABLE_AUTH := 1 542endif 543 544ifeq (${SPMC_AT_EL3}, 1) 545PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 546endif 547 548PSCI_OS_INIT_MODE := 1 549 550ifeq (${SPD},spmd) 551BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 552endif 553 554# Test specific macros, keep them at bottom of this file 555$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 556ifeq (${PLATFORM_TEST_EA_FFH}, 1) 557 ifeq (${FFH_SUPPORT}, 0) 558 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 559 endif 560 561endif 562 563$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 564ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 565 ifeq (${ENABLE_FEAT_RAS}, 0) 566 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 567 endif 568 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 569 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 570 endif 571endif 572 573$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 574ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 575 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 576 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 577 endif 578 ifeq (${ENABLE_SPMD_LP}, 0) 579 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 580 endif 581 ifeq (${ENABLE_FEAT_RAS}, 0) 582 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 583 endif 584 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 585 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 586 endif 587endif 588 589ifeq (${ERRATA_ABI_SUPPORT}, 1) 590include plat/arm/board/fvp/fvp_cpu_errata.mk 591endif 592 593# Build macro necessary for running SPM tests on FVP platform 594$(eval $(call add_define,PLAT_TEST_SPM)) 595 596ifeq (${LFA_SUPPORT},1) 597BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 598endif 599 600# This is set to 1 by default when the firmware update 601# support is enabled. Since the BL2 image is not updatable 602ifeq ($(PSA_FWU_SUPPORT),1) 603 SEPARATE_BL2_FIP := 1 604endif 605 606ifeq (${TRANSFER_LIST}, 0) 607ifeq (${SEPARATE_BL2_FIP},1) 608$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 609$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 610else 611$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 612$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 613endif 614endif 615