1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 32workaround_reset_end cortex_x2, CVE(2024, 5660) 33 34check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 35 36workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 37 ldr x0, =0x6 38 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 39 ldr x0, =0xF3A08002 40 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 41 ldr x0, =0xFFF0F7FE 42 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 43 ldr x0, =0x40000001003ff 44 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 45workaround_reset_end cortex_x2, ERRATUM(2002765) 46 47check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 48 49workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 50 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 51workaround_reset_end cortex_x2, ERRATUM(2017096) 52 53check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 54 55workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 56 sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 57 CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 58workaround_reset_end cortex_x2, ERRATUM(2058056) 59 60check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) 61 62workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 63 /* Apply instruction patching sequence */ 64 ldr x0, =0x3 65 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 66 ldr x0, =0xF3A08002 67 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 68 ldr x0, =0xFFF0F7FE 69 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 70 ldr x0, =0x10002001003FF 71 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 72 ldr x0, =0x4 73 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 74 ldr x0, =0xBF200000 75 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 76 ldr x0, =0xFFEF0000 77 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 78 ldr x0, =0x10002001003F3 79 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 80workaround_reset_end cortex_x2, ERRATUM(2081180) 81 82check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 83 84workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 85 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 86 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 87workaround_reset_end cortex_x2, ERRATUM(2083908) 88 89check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 90 91workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 92 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 93 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 94workaround_reset_end cortex_x2, ERRATUM(2147715) 95 96check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 97 98workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 99 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 100 101 /* Apply instruction patching sequence */ 102 ldr x0, =0x5 103 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 104 ldr x0, =0x10F600E000 105 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 106 ldr x0, =0x10FF80E000 107 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 108 ldr x0, =0x80000000003FF 109 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 110workaround_reset_end cortex_x2, ERRATUM(2216384) 111 112check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 113 114workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 115 /* Apply the workaround */ 116 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 117workaround_reset_end cortex_x2, ERRATUM(2282622) 118 119check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 120 121workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 122 /* Set bit 40 in CPUACTLR2_EL1 */ 123 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 124workaround_reset_end cortex_x2, ERRATUM(2371105) 125 126check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 127 128workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 129 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 130 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 131 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 132workaround_reset_end cortex_x2, ERRATUM(2742423) 133 134check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 135 136workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 137 /* dsb before isb of power down sequence */ 138 dsb sy 139workaround_runtime_end cortex_x2, ERRATUM(2768515) 140 141check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 142 143workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 144 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 145workaround_reset_end cortex_x2, ERRATUM(2778471) 146 147check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 148 149workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 150#if IMAGE_BL31 151 /* 152 * The Cortex-X2 generic vectors are overridden to apply errata 153 * mitigation on exception entry from lower ELs. 154 */ 155 override_vector_table wa_cve_vbar_cortex_x2 156#endif /* IMAGE_BL31 */ 157workaround_reset_end cortex_x2, CVE(2022, 23960) 158 159check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 160 161/* 162 * ERRATA_DSU_2313941 : 163 * The errata is defined in dsu_helpers.S but applies to cortex_x2 164 * as well. Henceforth creating symbolic names to the already existing errata 165 * workaround functions to get them registered under the Errata Framework. 166 */ 167.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941 168.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa 169add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 170 171 /* ---------------------------------------------------- 172 * HW will do the cache maintenance while powering down 173 * ---------------------------------------------------- 174 */ 175func cortex_x2_core_pwr_dwn 176 /* --------------------------------------------------- 177 * Enable CPU power down bit in power control register 178 * --------------------------------------------------- 179 */ 180 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 181 182 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV 183 isb 184 ret 185endfunc cortex_x2_core_pwr_dwn 186 187cpu_reset_func_start cortex_x2 188 /* Disable speculative loads */ 189 msr SSBS, xzr 190cpu_reset_func_end cortex_x2 191 192 /* --------------------------------------------- 193 * This function provides Cortex X2 specific 194 * register information for crash reporting. 195 * It needs to return with x6 pointing to 196 * a list of register names in ascii and 197 * x8 - x15 having values of registers to be 198 * reported. 199 * --------------------------------------------- 200 */ 201.section .rodata.cortex_x2_regs, "aS" 202cortex_x2_regs: /* The ascii list of register names to be reported */ 203 .asciz "cpuectlr_el1", "" 204 205func cortex_x2_cpu_reg_dump 206 adr x6, cortex_x2_regs 207 mrs x8, CORTEX_X2_CPUECTLR_EL1 208 ret 209endfunc cortex_x2_cpu_reg_dump 210 211declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 212 cortex_x2_reset_func, \ 213 cortex_x2_core_pwr_dwn 214