1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_ccm.h> 31 #include <imx8m_csu.h> 32 #include <imx8m_snvs.h> 33 #include <plat_common.h> 34 #include <plat_imx8.h> 35 36 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 37 38 /* 39 * Note: DRAM region is mapped with entire size available and uses MT_RW 40 * attributes. 41 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 42 * for explanation of this mapping scheme. 43 */ 44 static const mmap_region_t imx_mmap[] = { 45 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 46 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 47 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 48 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 49 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ 50 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */ 51 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */ 52 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */ 53 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */ 54 {0}, 55 }; 56 57 static const struct aipstz_cfg aipstz[] = { 58 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 59 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 60 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 61 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 62 {0}, 63 }; 64 65 static struct imx_rdc_cfg rdc[] = { 66 /* Master domain assignment */ 67 RDC_MDAn(RDC_MDA_M4, DID1), 68 69 /* peripherals domain permission */ 70 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 71 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 72 73 /* memory region */ 74 75 /* Sentinel */ 76 {0}, 77 }; 78 79 static const struct imx_csu_cfg csu_cfg[] = { 80 /* peripherals csl setting */ 81 CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED), 82 CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED), 83 CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED), 84 85 /* master HP0~1 */ 86 87 /* SA setting */ 88 CSU_SA(CSU_SA_M4, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_VPU, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_GPU, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_APBHDMA, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_ENET, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 102 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 103 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 104 CSU_SA(CSU_SA_LCDIF, NON_SEC_ACCESS, LOCKED), 105 CSU_SA(CSU_SA_CSI, NON_SEC_ACCESS, LOCKED), 106 107 /* HP control setting */ 108 109 /* Sentinel */ 110 {0} 111 }; 112 113 static entry_point_info_t bl32_image_ep_info; 114 static entry_point_info_t bl33_image_ep_info; 115 116 /* get SPSR for BL33 entry */ 117 static uint32_t get_spsr_for_bl33_entry(void) 118 { 119 unsigned long el_status; 120 unsigned long mode; 121 uint32_t spsr; 122 123 /* figure out what mode we enter the non-secure world */ 124 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 125 el_status &= ID_AA64PFR0_ELX_MASK; 126 127 mode = (el_status) ? MODE_EL2 : MODE_EL1; 128 129 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 130 return spsr; 131 } 132 133 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 134 u_register_t arg2, u_register_t arg3) 135 { 136 unsigned int console_base = IMX_BOOT_UART_BASE; 137 static console_t console; 138 int i, ret; 139 140 /* Enable CSU NS access permission */ 141 for (i = 0; i < 64; i++) { 142 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 143 } 144 145 imx_aipstz_init(aipstz); 146 147 if (console_base == 0U) { 148 console_base = imx8m_uart_get_base(); 149 } 150 151 imx_rdc_init(rdc, console_base); 152 153 imx_csu_init(csu_cfg); 154 155 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 156 IMX_CONSOLE_BAUDRATE, &console); 157 /* This console is only used for boot stage */ 158 console_set_scope(&console, CONSOLE_FLAG_BOOT); 159 160 imx8m_caam_init(); 161 162 /* 163 * tell BL3-1 where the non-secure software image is located 164 * and the entry state information. 165 */ 166 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 167 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 168 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 169 170 #if defined(SPD_opteed) || defined(SPD_trusty) 171 /* Populate entry point information for BL32 */ 172 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 173 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 174 bl32_image_ep_info.pc = BL32_BASE; 175 bl32_image_ep_info.spsr = 0; 176 177 /* Pass TEE base and size to bl33 */ 178 bl33_image_ep_info.args.arg1 = BL32_BASE; 179 bl33_image_ep_info.args.arg2 = BL32_SIZE; 180 181 #ifdef SPD_trusty 182 bl32_image_ep_info.args.arg0 = BL32_SIZE; 183 bl32_image_ep_info.args.arg1 = BL32_BASE; 184 #else 185 /* Make sure memory is clean */ 186 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 187 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 188 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 189 #endif 190 #endif 191 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, 192 &bl32_image_ep_info, &bl33_image_ep_info); 193 if (ret != 0) { 194 ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, 195 &bl32_image_ep_info, 196 &bl33_image_ep_info); 197 } 198 199 #if !defined(SPD_opteed) && !defined(SPD_trusty) 200 enable_snvs_privileged_access(); 201 #endif 202 } 203 204 #define MAP_BL31_TOTAL \ 205 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 206 #define MAP_BL31_RO \ 207 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 208 #define MAP_COHERENT_MEM \ 209 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 210 MT_DEVICE | MT_RW | MT_SECURE) 211 #define MAP_BL32_TOTAL \ 212 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 213 214 void bl31_plat_arch_setup(void) 215 { 216 const mmap_region_t bl_regions[] = { 217 MAP_BL31_TOTAL, 218 MAP_BL31_RO, 219 #if USE_COHERENT_MEM 220 MAP_COHERENT_MEM, 221 #endif 222 #if defined(SPD_opteed) || defined(SPD_trusty) 223 /* Map TEE memory */ 224 MAP_BL32_TOTAL, 225 #endif 226 {0} 227 }; 228 229 setup_page_tables(bl_regions, imx_mmap); 230 enable_mmu_el3(0); 231 } 232 233 void bl31_platform_setup(void) 234 { 235 generic_delay_timer_init(); 236 237 /* select the CKIL source to 32K OSC */ 238 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 239 240 /* Init the dram info */ 241 dram_info_init(SAVED_DRAM_TIMING_BASE); 242 243 plat_gic_driver_init(); 244 plat_gic_init(); 245 246 imx_gpc_init(); 247 } 248 249 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 250 { 251 if (type == NON_SECURE) 252 return &bl33_image_ep_info; 253 if (type == SECURE) 254 return &bl32_image_ep_info; 255 256 return NULL; 257 } 258 259 unsigned int plat_get_syscnt_freq2(void) 260 { 261 return COUNTER_FREQUENCY; 262 } 263 264 #ifdef SPD_trusty 265 void plat_trusty_set_boot_args(aapcs64_params_t *args) 266 { 267 args->arg0 = BL32_SIZE; 268 args->arg1 = BL32_BASE; 269 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 270 } 271 #endif 272