1/* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10#include <common/bl_common.h> 11#include <cortex_a78_ae.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21#if WORKAROUND_CVE_2022_23960 22 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae 23#endif /* WORKAROUND_CVE_2022_23960 */ 24 25/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 26workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 27 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46) 28workaround_reset_end cortex_a78_ae, CVE(2024, 5660) 29 30check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3) 31 32workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500 33 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 34workaround_reset_end cortex_a78_ae, ERRATUM(1941500) 35 36check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1) 37 38workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502 39 msr S3_6_c15_c8_0, xzr 40 ldr x0, =0x10E3900002 41 msr S3_6_c15_c8_2, x0 42 ldr x0, =0x10FFF00083 43 msr S3_6_c15_c8_3, x0 44 ldr x0, =0x2001003FF 45 msr S3_6_c15_c8_1, x0 46 47 mov x0, #1 48 msr S3_6_c15_c8_0, x0 49 ldr x0, =0x10E3800082 50 msr S3_6_c15_c8_2, x0 51 ldr x0, =0x10FFF00083 52 msr S3_6_c15_c8_3, x0 53 ldr x0, =0x2001003FF 54 msr S3_6_c15_c8_1, x0 55 56 mov x0, #2 57 msr S3_6_c15_c8_0, x0 58 ldr x0, =0x10E3800200 59 msr S3_6_c15_c8_2, x0 60 ldr x0, =0x10FFF003E0 61 msr S3_6_c15_c8_3, x0 62 ldr x0, =0x2001003FF 63 msr S3_6_c15_c8_1, x0 64workaround_reset_end cortex_a78_ae, ERRATUM(1951502) 65 66check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1) 67 68workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748 69 /* ------------------------------------------------------- 70 * Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to 71 * behave like PLD/PRFM LD and not cause invalidations to 72 * other PE caches. There might be a small performance 73 * degradation to this workaround for certain workloads 74 * that share data. 75 * ------------------------------------------------------- 76 */ 77 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0 78workaround_reset_end cortex_a78_ae, ERRATUM(2376748) 79 80check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 2) 81 82workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408 83 /* -------------------------------------------------------- 84 * Disable folding of demand requests into older prefetches 85 * with L2 miss requests outstanding by setting the 86 * CPUACTLR2_EL1[40] to 1. 87 * -------------------------------------------------------- 88 */ 89 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40 90workaround_reset_end cortex_a78_ae, ERRATUM(2395408) 91 92check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1) 93 94workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 95#if IMAGE_BL31 96 /* 97 * The Cortex-A78AE generic vectors are overridden to apply errata 98 * mitigation on exception entry from lower ELs. 99 */ 100 override_vector_table wa_cve_vbar_cortex_a78_ae 101#endif /* IMAGE_BL31 */ 102workaround_reset_end cortex_a78_ae, CVE(2022, 23960) 103 104check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 105 106cpu_reset_func_start cortex_a78_ae 107#if ENABLE_FEAT_AMU 108 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 109 sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT 110 111 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 112 sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT 113 114 /* Enable group0 counters */ 115 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 116 msr CPUAMCNTENSET0_EL0, x0 117 118 /* Enable group1 counters */ 119 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 120 msr CPUAMCNTENSET1_EL0, x0 121#endif 122cpu_reset_func_end cortex_a78_ae 123 124 /* ------------------------------------------------------- 125 * HW will do the cache maintenance while powering down 126 * ------------------------------------------------------- 127 */ 128func cortex_a78_ae_core_pwr_dwn 129 /* ------------------------------------------------------- 130 * Enable CPU power down bit in power control register 131 * ------------------------------------------------------- 132 */ 133 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 134 isb 135 ret 136endfunc cortex_a78_ae_core_pwr_dwn 137 138 /* ------------------------------------------------------- 139 * This function provides cortex_a78_ae specific 140 * register information for crash reporting. 141 * It needs to return with x6 pointing to 142 * a list of register names in ascii and 143 * x8 - x15 having values of registers to be 144 * reported. 145 * ------------------------------------------------------- 146 */ 147.section .rodata.cortex_a78_ae_regs, "aS" 148cortex_a78_ae_regs: /* The ascii list of register names to be reported */ 149 .asciz "cpuectlr_el1", "" 150 151func cortex_a78_ae_cpu_reg_dump 152 adr x6, cortex_a78_ae_regs 153 mrs x8, CORTEX_A78_CPUECTLR_EL1 154 ret 155endfunc cortex_a78_ae_cpu_reg_dump 156 157declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ 158 cortex_a78_ae_reset_func, \ 159 cortex_a78_ae_core_pwr_dwn 160