1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * Top-level SMC handler for Versal2 power management calls and 10 * IPI setup functions for communication with PMC. 11 */ 12 13 #include <errno.h> 14 #include <stdbool.h> 15 16 #include "../drivers/arm/gic/v3/gicv3_private.h" 17 18 #include <common/runtime_svc.h> 19 #include <drivers/arm/gicv3.h> 20 #include <lib/psci/psci.h> 21 #include <plat/arm/common/plat_arm.h> 22 #include <plat/common/platform.h> 23 24 #include <plat_private.h> 25 #include "pm_api_sys.h" 26 #include "pm_client.h" 27 #include "pm_ipi.h" 28 #include "pm_svc_main.h" 29 30 #define MODE 0x80000000U 31 32 #define INVALID_SGI 0xFFU 33 #define PM_INIT_SUSPEND_CB (30U) 34 #define PM_NOTIFY_CB (32U) 35 #define EVENT_CPU_PWRDWN (4U) 36 #define MBOX_SGI_SHARED_IPI (7U) 37 38 /** 39 * upper_32_bits - return bits 32-63 of a number 40 * @n: the number we're accessing 41 */ 42 #define upper_32_bits(n) ((uint32_t)((n) >> 32U)) 43 44 /** 45 * lower_32_bits - return bits 0-31 of a number 46 * @n: the number we're accessing 47 */ 48 #define lower_32_bits(n) ((uint32_t)((n) & 0xffffffffU)) 49 50 /** 51 * EXTRACT_SMC_ARGS - extracts 32-bit payloads from 64-bit SMC arguments 52 * @pm_arg: array of 32-bit payloads 53 * @x: array of 64-bit SMC arguments 54 */ 55 #define EXTRACT_ARGS(pm_arg, x) \ 56 for (uint32_t i = 0U; i < (PAYLOAD_ARG_CNT - 1U); i++) { \ 57 if ((i % 2U) != 0U) { \ 58 pm_arg[i] = lower_32_bits(x[(i / 2U) + 1U]); \ 59 } else { \ 60 pm_arg[i] = upper_32_bits(x[i / 2U]); \ 61 } \ 62 } 63 64 /* 1 sec of wait timeout for secondary core down */ 65 #define PWRDWN_WAIT_TIMEOUT (1000U) 66 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6) 67 68 /* pm_up = true - UP, pm_up = false - DOWN */ 69 static bool pm_up; 70 static uint32_t sgi = (uint32_t)INVALID_SGI; 71 static bool pwrdwn_req_received; 72 73 bool pm_pwrdwn_req_status(void) 74 { 75 return pwrdwn_req_received; 76 } 77 78 static void notify_os(void) 79 { 80 plat_ic_raise_ns_sgi((int)sgi, read_mpidr_el1()); 81 } 82 83 static uint64_t cpu_pwrdwn_req_handler(uint32_t id, uint32_t flags, 84 void *handle, void *cookie) 85 { 86 uint32_t cpu_id = plat_my_core_pos(); 87 88 VERBOSE("Powering down CPU %d\n", cpu_id); 89 90 /* Deactivate CPU power down SGI */ 91 plat_ic_end_of_interrupt(CPU_PWR_DOWN_REQ_INTR); 92 93 return (uint64_t) psci_cpu_off(); 94 } 95 96 /** 97 * raise_pwr_down_interrupt() - Callback function to raise SGI. 98 * @mpidr: MPIDR for the target CPU. 99 * 100 * Raise SGI interrupt to trigger the CPU power down sequence on all the 101 * online secondary cores. 102 */ 103 static void raise_pwr_down_interrupt(u_register_t mpidr) 104 { 105 plat_ic_raise_el3_sgi((int)CPU_PWR_DOWN_REQ_INTR, mpidr); 106 } 107 108 void request_cpu_pwrdwn(void) 109 { 110 int ret; 111 112 VERBOSE("CPU power down request received\n"); 113 114 /* Send powerdown request to online secondary core(s) */ 115 ret = psci_stop_other_cores(plat_my_core_pos(), (unsigned int)PWRDWN_WAIT_TIMEOUT, raise_pwr_down_interrupt); 116 if (ret != (int)PSCI_E_SUCCESS) { 117 ERROR("Failed to powerdown secondary core(s)\n"); 118 } 119 120 /* Clear IPI IRQ */ 121 pm_ipi_irq_clear(primary_proc); 122 123 /* Deactivate IPI IRQ */ 124 plat_ic_end_of_interrupt(PLAT_VERSAL_IPI_IRQ); 125 } 126 127 static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle, 128 void *cookie) 129 { 130 uint32_t payload[4] = {0}; 131 enum pm_ret_status ret; 132 uint32_t ipi_status, i; 133 134 VERBOSE("Received IPI FIQ from firmware\n"); 135 136 console_flush(); 137 (void)plat_ic_acknowledge_interrupt(); 138 139 /* Check status register for each IPI except PMC */ 140 for (i = IPI_ID_APU; i <= IPI_ID_5; i++) { 141 ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i); 142 143 /* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */ 144 if ((ipi_status & (uint32_t)IPI_MB_STATUS_RECV_PENDING) > (uint32_t) 0) { 145 plat_ic_raise_ns_sgi((int)MBOX_SGI_SHARED_IPI, read_mpidr_el1()); 146 break; 147 } 148 } 149 150 /* If PMC has not generated interrupt then end ISR */ 151 ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC); 152 if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == (uint32_t)0) { 153 plat_ic_end_of_interrupt(id); 154 goto end; 155 } 156 157 /* Handle PMC case */ 158 ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0); 159 if (ret != PM_RET_SUCCESS) { 160 payload[0] = (uint32_t) ret; 161 } 162 163 switch (payload[0]) { 164 case PM_INIT_SUSPEND_CB: 165 if (sgi != INVALID_SGI) { 166 notify_os(); 167 } 168 break; 169 case PM_NOTIFY_CB: 170 if (sgi != INVALID_SGI) { 171 if ((payload[2] == EVENT_CPU_PWRDWN) && 172 (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) { 173 if (pwrdwn_req_received) { 174 pwrdwn_req_received = false; 175 request_cpu_pwrdwn(); 176 (void)psci_cpu_off(); 177 break; 178 } else { 179 /* No action needed, added for MISRA 180 * complaince 181 */ 182 } 183 pwrdwn_req_received = true; 184 185 } else { 186 /* No action needed, added for MISRA 187 * complaince 188 */ 189 } 190 notify_os(); 191 } else if ((payload[2] == EVENT_CPU_PWRDWN) && 192 (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) { 193 request_cpu_pwrdwn(); 194 (void)psci_cpu_off(); 195 } else { 196 /* No action needed, added for MISRA 197 * complaince 198 */ 199 } 200 break; 201 case (uint32_t) PM_RET_ERROR_INVALID_CRC: 202 pm_ipi_irq_clear(primary_proc); 203 WARN("Invalid CRC in the payload\n"); 204 break; 205 206 default: 207 pm_ipi_irq_clear(primary_proc); 208 WARN("Invalid IPI payload\n"); 209 break; 210 } 211 212 /* Clear FIQ */ 213 plat_ic_end_of_interrupt(id); 214 215 end: 216 return 0; 217 } 218 219 /** 220 * pm_register_sgi() - PM register the IPI interrupt. 221 * @sgi_num: SGI number to be used for communication. 222 * @reset: Reset to invalid SGI when reset=1. 223 * 224 * Return: On success, the initialization function must return 0. 225 * Any other return value will cause the framework to ignore 226 * the service. 227 * 228 * Update the SGI number to be used. 229 * 230 */ 231 int32_t pm_register_sgi(uint32_t sgi_num, uint32_t reset) 232 { 233 int32_t ret; 234 235 if (reset == 1U) { 236 sgi = INVALID_SGI; 237 ret = 0; 238 goto end; 239 } 240 241 if (sgi != INVALID_SGI) { 242 ret = -EBUSY; 243 goto end; 244 } 245 246 if (sgi_num >= GICV3_MAX_SGI_TARGETS) { 247 ret = -EINVAL; 248 goto end; 249 } 250 251 sgi = (uint32_t)sgi_num; 252 ret = 0; 253 end: 254 return ret; 255 } 256 257 /** 258 * pm_setup() - PM service setup. 259 * 260 * Return: On success, the initialization function must return 0. 261 * Any other return value will cause the framework to ignore 262 * the service. 263 * 264 * Initialization functions for Versal power management for 265 * communicaton with PMC. 266 * 267 * Called from sip_svc_setup initialization function with the 268 * rt_svc_init signature. 269 * 270 */ 271 int32_t pm_setup(void) 272 { 273 int32_t ret = 0; 274 275 pm_ipi_init(primary_proc); 276 pm_up = true; 277 pwrdwn_req_received = false; 278 279 /* register SGI handler for CPU power down request */ 280 ret = request_intr_type_el3(CPU_PWR_DOWN_REQ_INTR, cpu_pwrdwn_req_handler); 281 if (ret != 0) { 282 WARN("BL31: registering SGI interrupt failed\n"); 283 } 284 285 /* 286 * Enable IPI IRQ 287 * assume the rich OS is OK to handle callback IRQs now. 288 * Even if we were wrong, it would not enable the IRQ in 289 * the GIC. 290 */ 291 pm_ipi_irq_enable(primary_proc); 292 293 ret = request_intr_type_el3(PLAT_VERSAL_IPI_IRQ, ipi_fiq_handler); 294 if (ret != 0) { 295 WARN("BL31: registering IPI interrupt failed\n"); 296 } 297 298 gicd_write_irouter(gicv3_driver_data->gicd_base, PLAT_VERSAL_IPI_IRQ, MODE); 299 300 /* Register for idle callback during force power down/restart */ 301 ret = (int32_t)pm_register_notifier(primary_proc->node_id, EVENT_CPU_PWRDWN, 302 0x0U, 0x1U, SECURE_FLAG); 303 if (ret != 0) { 304 WARN("BL31: registering idle callback for restart/force power down failed\n"); 305 } 306 307 return ret; 308 } 309 310 /** 311 * eemi_psci_debugfs_handler() - EEMI API invoked from PSCI. 312 * @api_id: identifier for the API being called. 313 * @pm_arg: pointer to the argument data for the API call. 314 * @handle: Pointer to caller's context structure. 315 * @security_flag: SECURE_FLAG or NON_SECURE_FLAG. 316 * 317 * These EEMI APIs performs CPU specific power management tasks. 318 * These EEMI APIs are invoked either from PSCI or from debugfs in kernel. 319 * These calls require CPU specific processing before sending IPI request to 320 * Platform Management Controller. For example enable/disable CPU specific 321 * interrupts. This requires separate handler for these calls and may not be 322 * handled using common eemi handler. 323 * 324 * Return: If EEMI API found then, uintptr_t type address, else 0. 325 * 326 */ 327 static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, uint32_t *pm_arg, 328 void *handle, uint32_t security_flag) 329 { 330 enum pm_ret_status ret; 331 332 switch (api_id) { 333 334 case (uint32_t)PM_SELF_SUSPEND: 335 ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 336 pm_arg[3], security_flag); 337 SMC_RET1(handle, (u_register_t)ret); 338 339 case (uint32_t)PM_FORCE_POWERDOWN: 340 ret = pm_force_powerdown(pm_arg[0], (uint8_t)pm_arg[1], security_flag); 341 SMC_RET1(handle, (u_register_t)ret); 342 343 case (uint32_t)PM_REQ_SUSPEND: 344 ret = pm_req_suspend(pm_arg[0], (uint8_t)pm_arg[1], pm_arg[2], 345 pm_arg[3], security_flag); 346 SMC_RET1(handle, (u_register_t)ret); 347 348 case (uint32_t)PM_ABORT_SUSPEND: 349 ret = pm_abort_suspend(pm_arg[0], security_flag); 350 SMC_RET1(handle, (u_register_t)ret); 351 352 case (uint32_t)PM_SYSTEM_SHUTDOWN: 353 ret = pm_system_shutdown(pm_arg[0], pm_arg[1], security_flag); 354 SMC_RET1(handle, (u_register_t)ret); 355 356 default: 357 return (uintptr_t)0; 358 } 359 } 360 361 /** 362 * TF_A_specific_handler() - SMC handler for TF-A specific functionality. 363 * @api_id: identifier for the API being called. 364 * @pm_arg: pointer to the argument data for the API call. 365 * @handle: Pointer to caller's context structure. 366 * @security_flag: SECURE_FLAG or NON_SECURE_FLAG. 367 * 368 * These EEMI calls performs functionality that does not require 369 * IPI transaction. The handler ends in TF-A and returns requested data to 370 * kernel from TF-A. 371 * 372 * Return: If TF-A specific API found then, uintptr_t type address, else 0 373 * 374 */ 375 static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg, 376 void *handle, uint32_t security_flag) 377 { 378 switch (api_id) { 379 380 case TF_A_FEATURE_CHECK: 381 { 382 enum pm_ret_status ret; 383 uint32_t result[PAYLOAD_ARG_CNT] = {0U}; 384 385 ret = eemi_feature_check(pm_arg[0], result); 386 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U)); 387 } 388 389 case TF_A_PM_REGISTER_SGI: 390 { 391 int32_t ret; 392 393 ret = pm_register_sgi(pm_arg[0], pm_arg[1]); 394 if (ret != 0) { 395 SMC_RET1(handle, (uint32_t)PM_RET_ERROR_ARGS); 396 } 397 398 SMC_RET1(handle, (uint32_t)PM_RET_SUCCESS); 399 } 400 401 case PM_GET_CALLBACK_DATA: 402 { 403 uint32_t result[4] = {0}; 404 enum pm_ret_status ret; 405 406 ret = pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag, 1U); 407 if (ret != PM_RET_SUCCESS) { 408 result[0] = (uint32_t) ret; 409 } 410 411 SMC_RET2(handle, 412 (uint64_t)result[0] | ((uint64_t)result[1] << 32U), 413 (uint64_t)result[2] | ((uint64_t)result[3] << 32U)); 414 } 415 416 case PM_GET_TRUSTZONE_VERSION: 417 SMC_RET1(handle, ((uint64_t)PM_RET_SUCCESS) | 418 (((uint64_t)TZ_VERSION) << 32U)); 419 420 default: 421 return (uintptr_t)0U; 422 } 423 } 424 425 /** 426 * eemi_api_handler() - Prepare EEMI payload and perform IPI transaction. 427 * @api_id: identifier for the API being called. 428 * @pm_arg: pointer to the argument data for the API call. 429 * @handle: Pointer to caller's context structure. 430 * @security_flag: SECURE_FLAG or NON_SECURE_FLAG. 431 * 432 * EEMI - Embedded Energy Management Interface is AMD-Xilinx proprietary 433 * protocol to allow communication between power management controller and 434 * different processing clusters. 435 * 436 * This handler prepares EEMI protocol payload received from kernel and performs 437 * IPI transaction. 438 * 439 * Return: If EEMI API found then, uintptr_t type address, else 0 440 */ 441 static uintptr_t eemi_api_handler(uint32_t api_id, const uint32_t *pm_arg, 442 void *handle, uint32_t security_flag) 443 { 444 enum pm_ret_status ret; 445 uint32_t buf[RET_PAYLOAD_ARG_CNT] = {0U}; 446 uint32_t payload[PAYLOAD_ARG_CNT] = {0U}; 447 uint32_t module_id; 448 449 module_id = (api_id & MODULE_ID_MASK) >> 8U; 450 451 PM_PACK_PAYLOAD7(payload, module_id, security_flag, api_id, 452 pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], 453 pm_arg[4], pm_arg[5]); 454 455 ret = pm_ipi_send_sync(primary_proc, payload, (uint32_t *)buf, 456 RET_PAYLOAD_ARG_CNT); 457 458 SMC_RET4(handle, (uint64_t)ret | ((uint64_t)buf[0] << 32U), 459 (uint64_t)buf[1] | ((uint64_t)buf[2] << 32U), 460 (uint64_t)buf[3] | ((uint64_t)buf[4] << 32U), 461 (uint64_t)buf[5]); 462 } 463 464 /** 465 * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. 466 * @smc_fid: Function Identifier. 467 * @x1: SMC64 Arguments from kernel. 468 * @x2: SMC64 Arguments from kernel. 469 * @x3: SMC64 Arguments from kernel (upper 32-bits). 470 * @x4: Unused. 471 * @cookie: Unused. 472 * @handle: Pointer to caller's context structure. 473 * @flags: SECURE_FLAG or NON_SECURE_FLAG. 474 * 475 * Return: Unused. 476 * 477 * Determines that smc_fid is valid and supported PM SMC Function ID from the 478 * list of pm_api_ids, otherwise completes the request with 479 * the unknown SMC Function ID. 480 * 481 * The SMC calls for PM service are forwarded from SIP Service SMC handler 482 * function with rt_svc_handle signature. 483 * 484 */ 485 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 486 uint64_t x4, const void *cookie, void *handle, uint64_t flags) 487 { 488 uintptr_t ret; 489 uint32_t pm_arg[PAYLOAD_ARG_CNT] = {0}; 490 uint32_t security_flag = NON_SECURE_FLAG; 491 uint32_t api_id; 492 bool status = false, status_tmp = false; 493 uint64_t x[4] = {x1, x2, x3, x4}; 494 495 /* Handle case where PM wasn't initialized properly */ 496 if (pm_up == false) { 497 SMC_RET1(handle, SMC_UNK); 498 } 499 500 /* 501 * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as secure (0) 502 * if smc called is secure 503 * 504 * Add redundant macro call to immune the code from glitches 505 */ 506 SECURE_REDUNDANT_CALL(status, status_tmp, is_caller_secure, flags); 507 if ((status != false) && (status_tmp != false)) { 508 security_flag = SECURE_FLAG; 509 } 510 511 if ((smc_fid & FUNCID_NUM_MASK) == PASS_THROUGH_FW_CMD_ID) { 512 api_id = lower_32_bits(x[0]); 513 514 EXTRACT_ARGS(pm_arg, x); 515 516 return eemi_api_handler(api_id, pm_arg, handle, security_flag); 517 } 518 519 pm_arg[0] = (uint32_t)x1; 520 pm_arg[1] = (uint32_t)(x1 >> 32U); 521 pm_arg[2] = (uint32_t)x2; 522 pm_arg[3] = (uint32_t)(x2 >> 32U); 523 pm_arg[4] = (uint32_t)x3; 524 (void)(x4); 525 api_id = smc_fid & FUNCID_NUM_MASK; 526 527 ret = eemi_psci_debugfs_handler(api_id, pm_arg, handle, (uint32_t)flags); 528 if (ret != (uintptr_t)0) 529 goto error; 530 531 ret = TF_A_specific_handler(api_id, pm_arg, handle, security_flag); 532 if (ret != (uintptr_t)0) 533 goto error; 534 535 error: 536 return ret; 537 } 538