1 /* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DSU_DEF_H 8 #define DSU_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************** 13 * DSU Cluster Configuration registers definitions 14 ********************************************************************/ 15 #define CLUSTERCFR_EL1 S3_0_C15_C3_0 16 17 #define CLUSTERCFR_ACP_SHIFT U(11) 18 19 /******************************************************************** 20 * DSU Cluster Main Revision ID registers definitions 21 ********************************************************************/ 22 #define CLUSTERIDR_EL1 S3_0_C15_C3_1 23 24 #define CLUSTERIDR_REV_SHIFT U(0) 25 #define CLUSTERIDR_REV_BITS U(4) 26 #define CLUSTERIDR_VAR_SHIFT U(4) 27 #define CLUSTERIDR_VAR_BITS U(4) 28 29 #define CLUSTERREVIDR_EL1 S3_0_C15_C3_2 30 31 /******************************************************************** 32 * DSU Cluster Auxiliary Control registers definitions 33 ********************************************************************/ 34 #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 35 36 /* CLUSTERPWRCTLR_EL1 register definitions */ 37 #define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5 38 #define CLUSTERPWRCTLR_FUNCRET_WIDTH U(3) 39 #define CLUSTERPWRCTLR_FUNCRET_SHIFT U(0) 40 #define CLUSTERPWRCTLR_FUNCRET_RESET U(0) 41 #define CLUSTERPWRCTLR_CACHEPWR_WIDTH U(4) 42 #define CLUSTERPWRCTLR_CACHEPWR_SHIFT U(4) 43 #define CLUSTERPWRCTLR_CACHEPWR_RESET U(7) 44 45 #define CLUSTERACTLR_EL1_ASSERT_CBUSY (ULL(1) << 8) 46 #define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) 47 #define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) 48 #define CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY (ULL(3) << 20) 49 50 /* CLUSTERPWRDN_EL1 register definitions */ 51 #define CLUSTERPWRDN_PWRDN_WIDTH U(1) 52 #define CLUSTERPWRDN_PWRDN_SHIFT U(0) 53 #define CLUSTERPWRDN_MEMRET_WIDTH U(1) 54 #define CLUSTERPWRDN_MEMRET_SHIFT U(1) 55 56 /******************************************************************** 57 * Masks applied for DSU errata workarounds 58 ********************************************************************/ 59 #define DSU_ERRATA_936184_MASK (U(0x3) << 15) 60 61 #define CPUCFR_EL1 S3_0_C15_C0_0 62 /* SCU bit of CPU Configuration Register, EL1 */ 63 #define SCU_SHIFT U(2) 64 65 #ifndef __ASSEMBLER__ 66 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrctlr_el1, CLUSTERPWRCTLR_EL1); 67 68 /* --------------------------------------------- 69 * controls power features of the cluster 70 * 1. Cache portion power not request 71 * 2. Disable the retention circuit 72 * --------------------------------------------- 73 */ 74 static inline void dsu_pwr_dwn(void) 75 { 76 write_clusterpwrctlr_el1(0); 77 isb(); 78 } 79 #endif 80 #endif /* DSU_DEF_H */ 81