1# 2# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 5# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 6# 7# SPDX-License-Identifier: BSD-3-Clause 8 9override ERRATA_A53_855873 := 1 10ERRATA_A53_1530924 := 1 11override PROGRAMMABLE_RESET_ADDRESS := 1 12PSCI_EXTENDED_STATE_ID := 1 13A53_DISABLE_NON_TEMPORAL_HINT := 0 14SEPARATE_CODE_AND_RODATA := 1 15ZYNQMP_WDT_RESTART := 0 16IPI_CRC_CHECK := 0 17override RESET_TO_BL31 := 1 18override WARMBOOT_ENABLE_DCACHE_EARLY := 1 19ENABLE_LTO := 1 20 21EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) 22 23# pncd SPD requires secure SGI to be handled at EL1 24ifeq (${SPD}, $(filter ${SPD},pncd tspd opteed)) 25ifeq (${ZYNQMP_WDT_RESTART},1) 26$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible") 27endif 28override GICV2_G0_FOR_EL3 := 0 29else 30override GICV2_G0_FOR_EL3 := 1 31endif 32 33# Do not enable SVE 34ENABLE_SVE_FOR_NS := 0 35 36WORKAROUND_CVE_2017_5715 := 0 37 38ifdef ZYNQMP_ATF_MEM_BASE 39 $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE)) 40 41 ifndef ZYNQMP_ATF_MEM_SIZE 42 $(error "ZYNQMP_ATF_MEM_BASE defined without ZYNQMP_ATF_MEM_SIZE") 43 endif 44 $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE)) 45 46 ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 47 $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE)) 48 endif 49 50 # enable assert() when TF-A runs from DDR memory. 51 ENABLE_ASSERTIONS := 1 52 53endif 54 55ifdef ZYNQMP_BL32_MEM_BASE 56 $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE)) 57 58 ifndef ZYNQMP_BL32_MEM_SIZE 59 $(error "ZYNQMP_BL32_MEM_BASE defined without ZYNQMP_BL32_MEM_SIZE") 60 endif 61 $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE)) 62endif 63 64 65ifdef ZYNQMP_WDT_RESTART 66 $(eval $(call add_define,ZYNQMP_WDT_RESTART)) 67endif 68 69ifdef ZYNQMP_IPI_CRC_CHECK 70 $(warning "ZYNQMP_IPI_CRC_CHECK macro is deprecated...instead please use IPI_CRC_CHECK.") 71endif 72 73ifdef IPI_CRC_CHECK 74 $(eval $(call add_define,IPI_CRC_CHECK)) 75endif 76 77ifdef ZYNQMP_SECURE_EFUSES 78 $(eval $(call add_define,ZYNQMP_SECURE_EFUSES)) 79endif 80 81ifdef XILINX_OF_BOARD_DTB_ADDR 82$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 83endif 84 85PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 86 -Iinclude/plat/arm/common/aarch64/ \ 87 -Iplat/xilinx/common/include/ \ 88 -Iplat/xilinx/common/ipi_mailbox_service/ \ 89 -Iplat/xilinx/zynqmp/include/ \ 90 -Iplat/xilinx/zynqmp/pm_service/ \ 91 92include lib/libfdt/libfdt.mk 93# Include GICv2 driver files 94include drivers/arm/gic/v2/gicv2.mk 95include lib/xlat_tables_v2/xlat_tables.mk 96 97PLAT_BL_COMMON_SOURCES := drivers/arm/dcc/dcc_console.c \ 98 drivers/delay_timer/delay_timer.c \ 99 drivers/delay_timer/generic_delay_timer.c \ 100 ${GICV2_SOURCES} \ 101 drivers/cadence/uart/aarch64/cdns_console.S \ 102 plat/arm/common/arm_cci.c \ 103 plat/arm/common/arm_common.c \ 104 plat/common/plat_gicv2_base.c \ 105 plat/common/plat_gicv2.c \ 106 plat/xilinx/common/ipi.c \ 107 plat/xilinx/zynqmp/zynqmp_ipi.c \ 108 plat/common/aarch64/crash_console_helpers.S \ 109 plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \ 110 plat/xilinx/zynqmp/aarch64/zynqmp_common.c \ 111 ${XLAT_TABLES_LIB_SRCS} 112 113ZYNQMP_CONSOLE ?= cadence 114ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc dtb none)) 115else 116 $(error "Please define ZYNQMP_CONSOLE") 117endif 118$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE})) 119 120# Runtime console in default console in DEBUG build 121ifeq ($(DEBUG), 1) 122CONSOLE_RUNTIME ?= $(ZYNQMP_CONSOLE) 123endif 124 125# Runtime console 126ifdef CONSOLE_RUNTIME 127ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},cadence cadence0 cadence1 dcc dtb)) 128$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 129else 130$(error "Please define CONSOLE_RUNTIME") 131endif 132endif 133 134# Build PM code as a Library 135include plat/xilinx/zynqmp/libpm.mk 136 137BL31_SOURCES += drivers/arm/cci/cci.c \ 138 lib/cpus/aarch64/aem_generic.S \ 139 lib/cpus/aarch64/cortex_a53.S \ 140 plat/common/plat_psci_common.c \ 141 common/fdt_fixup.c \ 142 common/fdt_wrappers.c \ 143 ${LIBFDT_SRCS} \ 144 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 145 plat/xilinx/common/plat_startup.c \ 146 plat/xilinx/common/plat_console.c \ 147 plat/xilinx/common/plat_fdt.c \ 148 plat/xilinx/zynqmp/bl31_zynqmp_setup.c \ 149 plat/xilinx/zynqmp/plat_psci.c \ 150 plat/xilinx/zynqmp/plat_zynqmp.c \ 151 plat/xilinx/zynqmp/plat_topology.c \ 152 plat/xilinx/zynqmp/sip_svc_setup.c 153 154ifeq (${SDEI_SUPPORT},1) 155BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \ 156 plat/xilinx/zynqmp/zynqmp_sdei.c 157endif 158 159BL31_CPPFLAGS += -fno-jump-tables 160TF_CFLAGS_aarch64 += -mbranch-protection=none 161 162ifdef CUSTOM_PKG_PATH 163include $(CUSTOM_PKG_PATH)/custom_pkg.mk 164else 165BL31_SOURCES += plat/xilinx/common/custom_sip_svc.c 166endif 167 168ifneq (${RESET_TO_BL31},1) 169 $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.") 170endif 171