1 /* 2 * Copyright (c) 2013-2025, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <bl31/interrupt_mgmt.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gicv3.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_helpers.h> 19 #include <platform_def.h> 20 21 #include "rcar_def.h" 22 #include "rcar_private.h" 23 #include "rcar_version.h" 24 25 const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN] 26 __section("ro") = VERSION_OF_RENESAS; 27 28 #define RCAR_DCACHE MT_MEMORY 29 30 #define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \ 31 RCAR_SHARED_MEM_SIZE, \ 32 MT_MEMORY | MT_RW | MT_SECURE) 33 34 #define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \ 35 DEVICE_RCAR_SIZE, \ 36 MT_DEVICE | MT_RW | MT_SECURE) 37 38 #define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \ 39 DEVICE_RCAR_SIZE2, \ 40 MT_DEVICE | MT_RW | MT_SECURE) 41 42 #define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \ 43 RCAR_BL31_CRASH_SIZE, \ 44 MT_MEMORY | MT_RW | MT_SECURE) 45 46 #define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \ 47 DEVICE_SRAM_SIZE, \ 48 MT_MEMORY | MT_RO | MT_SECURE) 49 50 #define MAP_SRAM_DATA_STACK MAP_REGION_FLAT(DEVICE_SRAM_DATA_BASE, \ 51 (DEVICE_SRAM_DATA_SIZE + \ 52 DEVICE_SRAM_STACK_SIZE), \ 53 MT_MEMORY | MT_RW | MT_SECURE) 54 55 static const mmap_region_t rcar_mmap[] = { 56 MAP_SHARED_RAM, /* 0x46422000 - 0x46422FFF Shared ram area */ 57 MAP_ATFW_CRASH, /* 0x4643F000 - 0x4643FFFF Stack for Crash Log */ 58 MAP_DEVICE_RCAR, /* 0xE6000000 - 0xE62FFFFF SoC registers area */ 59 MAP_SRAM, /* 0xE6342000 - 0xE6343FFF System RAM code area */ 60 MAP_SRAM_DATA_STACK, /* 0xE6344000 - 0xE6344FFF System RAM data & stack area */ 61 MAP_DEVICE_RCAR2, /* 0xE6370000 - 0xFFFFFFFF SoC registers area 2 */ 62 { 0 } 63 }; 64 65 CASSERT((ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS) <= MAX_MMAP_REGIONS, 66 assert_max_mmap_regions); 67 68 /* 69 * Macro generating the code for the function setting up the pagetables as per 70 * the platform memory map & initialize the mmu, for the given exception level 71 */ 72 void rcar_configure_mmu_el3(uintptr_t total_base, 73 size_t total_size, 74 uintptr_t ro_start, 75 uintptr_t ro_limit) 76 { 77 mmap_add_region(total_base, total_base, total_size, 78 RCAR_DCACHE | MT_RW | MT_SECURE); 79 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, 80 RCAR_DCACHE | MT_RO | MT_SECURE); 81 mmap_add(rcar_mmap); 82 83 init_xlat_tables(); 84 enable_mmu_el3(0); 85 } 86 87 unsigned int plat_get_syscnt_freq2(void) 88 { 89 unsigned int freq; 90 91 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 92 if (freq == 0) 93 panic(); 94 95 return freq; 96 } 97 98 unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 99 { 100 return plat_renesas_calc_core_pos(mpidr); 101 } 102