1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/fpmr.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 } 153 154 #if ENABLE_RME && IMAGE_BL31 155 /****************************************************************************** 156 * This function performs initializations that are specific to REALM state 157 * and updates the cpu context specified by 'ctx'. 158 * 159 * NOTE: any changes to this function must be verified by an RMMD maintainer. 160 *****************************************************************************/ 161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 162 { 163 u_register_t scr_el3; 164 el3_state_t *state; 165 el2_sysregs_t *el2_ctx; 166 167 state = get_el3state_ctx(ctx); 168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 169 el2_ctx = get_el2_sysregs_ctx(ctx); 170 171 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 172 173 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 174 175 /* CSV2 version 2 and above */ 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 if (is_feat_sctlr2_supported()) { 182 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 183 * SCTLR2_ELx registers. 184 */ 185 scr_el3 |= SCR_SCTLR2En_BIT; 186 } 187 188 if (is_feat_d128_supported()) { 189 /* 190 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 191 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 192 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 193 */ 194 scr_el3 |= SCR_D128En_BIT; 195 } 196 197 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 198 199 if (is_feat_fgt2_supported()) { 200 fgt2_enable(ctx); 201 } 202 203 if (is_feat_debugv8p9_supported()) { 204 debugv8p9_extended_bp_wp_enable(ctx); 205 } 206 207 if (is_feat_brbe_supported()) { 208 brbe_enable(ctx); 209 } 210 211 /* 212 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 213 */ 214 if (is_feat_sme_supported()) { 215 sme_enable(ctx); 216 } 217 218 if (is_feat_spe_supported()) { 219 spe_disable_realm(ctx); 220 } 221 222 if (is_feat_trbe_supported()) { 223 trbe_disable_realm(ctx); 224 } 225 } 226 #endif /* ENABLE_RME && IMAGE_BL31 */ 227 228 /****************************************************************************** 229 * This function performs initializations that are specific to NON-SECURE state 230 * and updates the cpu context specified by 'ctx'. 231 *****************************************************************************/ 232 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 233 { 234 u_register_t scr_el3; 235 el3_state_t *state; 236 237 state = get_el3state_ctx(ctx); 238 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 239 240 /* SCR_NS: Set the NS bit */ 241 scr_el3 |= SCR_NS_BIT; 242 243 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 244 if (is_feat_mte2_supported()) { 245 scr_el3 |= SCR_ATA_BIT; 246 } 247 248 /* 249 * Pointer Authentication feature, if present, is always enabled by 250 * default for Non secure lower exception levels. We do not have an 251 * explicit flag to set it. To prevent the leakage between the worlds 252 * during world switch, we enable it only for the non-secure world. 253 * 254 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 255 * exception levels of secure and realm worlds. 256 * 257 * If the Secure/realm world wants to use pointer authentication, 258 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 259 * it will be enabled globally for all the contexts. 260 * 261 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 262 * other than EL3 263 * 264 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 265 * than EL3 266 */ 267 if (!is_ctx_pauth_supported()) { 268 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 269 } 270 271 #if HANDLE_EA_EL3_FIRST_NS 272 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 273 scr_el3 |= SCR_EA_BIT; 274 #endif 275 276 #if RAS_TRAP_NS_ERR_REC_ACCESS 277 /* 278 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 279 * and RAS ERX registers from EL1 and EL2(from any security state) 280 * are trapped to EL3. 281 * Set here to trap only for NS EL1/EL2 282 */ 283 scr_el3 |= SCR_TERR_BIT; 284 #endif 285 286 /* CSV2 version 2 and above */ 287 if (is_feat_csv2_2_supported()) { 288 /* Enable access to the SCXTNUM_ELx registers. */ 289 scr_el3 |= SCR_EnSCXT_BIT; 290 } 291 292 #ifdef IMAGE_BL31 293 /* 294 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 295 * indicated by the interrupt routing model for BL31. 296 */ 297 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 298 #endif 299 300 if (is_feat_the_supported()) { 301 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 302 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 303 */ 304 scr_el3 |= SCR_RCWMASKEn_BIT; 305 } 306 307 if (is_feat_sctlr2_supported()) { 308 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 309 * SCTLR2_ELx registers. 310 */ 311 scr_el3 |= SCR_SCTLR2En_BIT; 312 } 313 314 if (is_feat_d128_supported()) { 315 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 316 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 317 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 318 */ 319 scr_el3 |= SCR_D128En_BIT; 320 } 321 322 if (is_feat_fpmr_supported()) { 323 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 324 * register. 325 */ 326 scr_el3 |= SCR_EnFPM_BIT; 327 } 328 329 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 330 331 /* Initialize EL2 context registers */ 332 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 333 if (is_feat_hcx_supported()) { 334 /* 335 * Initialize register HCRX_EL2 with its init value. 336 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 337 * chance that this can lead to unexpected behavior in lower 338 * ELs that have not been updated since the introduction of 339 * this feature if not properly initialized, especially when 340 * it comes to those bits that enable/disable traps. 341 */ 342 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 343 HCRX_EL2_INIT_VAL); 344 } 345 346 if (is_feat_fgt_supported()) { 347 /* 348 * Initialize HFG*_EL2 registers with a default value so legacy 349 * systems unaware of FEAT_FGT do not get trapped due to their lack 350 * of initialization for this feature. 351 */ 352 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 353 HFGITR_EL2_INIT_VAL); 354 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 355 HFGRTR_EL2_INIT_VAL); 356 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 357 HFGWTR_EL2_INIT_VAL); 358 } 359 #else 360 /* Initialize EL1 context registers */ 361 setup_el1_context(ctx, ep); 362 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 363 364 manage_extensions_nonsecure(ctx); 365 } 366 367 /******************************************************************************* 368 * The following function performs initialization of the cpu_context 'ctx' 369 * for first use that is common to all security states, and sets the 370 * initial entrypoint state as specified by the entry_point_info structure. 371 * 372 * The EE and ST attributes are used to configure the endianness and secure 373 * timer availability for the new execution context. 374 ******************************************************************************/ 375 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 376 { 377 u_register_t scr_el3; 378 u_register_t mdcr_el3; 379 el3_state_t *state; 380 gp_regs_t *gp_regs; 381 382 state = get_el3state_ctx(ctx); 383 384 /* Clear any residual register values from the context */ 385 zeromem(ctx, sizeof(*ctx)); 386 387 /* 388 * The lower-EL context is zeroed so that no stale values leak to a world. 389 * It is assumed that an all-zero lower-EL context is good enough for it 390 * to boot correctly. However, there are very few registers where this 391 * is not true and some values need to be recreated. 392 */ 393 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 394 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 395 396 /* 397 * These bits are set in the gicv3 driver. Losing them (especially the 398 * SRE bit) is problematic for all worlds. Henceforth recreate them. 399 */ 400 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 401 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 402 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 403 404 /* 405 * The actlr_el2 register can be initialized in platform's reset handler 406 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 407 */ 408 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 409 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 410 411 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 412 scr_el3 = SCR_RESET_VAL; 413 414 /* 415 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 416 * EL2, EL1 and EL0 are not trapped to EL3. 417 * 418 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 419 * EL2, EL1 and EL0 are not trapped to EL3. 420 * 421 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 422 * both Security states and both Execution states. 423 * 424 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 425 * Non-secure memory. 426 */ 427 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 428 429 scr_el3 |= SCR_SIF_BIT; 430 431 /* 432 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 433 * Exception level as specified by SPSR. 434 */ 435 if (GET_RW(ep->spsr) == MODE_RW_64) { 436 scr_el3 |= SCR_RW_BIT; 437 } 438 439 /* 440 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 441 * Secure timer registers to EL3, from AArch64 state only, if specified 442 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 443 * bit always behaves as 1 (i.e. secure physical timer register access 444 * is not trapped) 445 */ 446 if (EP_GET_ST(ep->h.attr) != 0U) { 447 scr_el3 |= SCR_ST_BIT; 448 } 449 450 /* 451 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 452 * SCR_EL3.HXEn. 453 */ 454 if (is_feat_hcx_supported()) { 455 scr_el3 |= SCR_HXEn_BIT; 456 } 457 458 /* 459 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 460 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 461 * SCR_EL3.EnAS0. 462 */ 463 if (is_feat_ls64_accdata_supported()) { 464 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 465 } 466 467 /* 468 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 469 * registers are trapped to EL3. 470 */ 471 if (is_feat_rng_trap_supported()) { 472 scr_el3 |= SCR_TRNDR_BIT; 473 } 474 475 #if FAULT_INJECTION_SUPPORT 476 /* Enable fault injection from lower ELs */ 477 scr_el3 |= SCR_FIEN_BIT; 478 #endif 479 480 /* 481 * Enable Pointer Authentication globally for all the worlds. 482 * 483 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 484 * other than EL3 485 * 486 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 487 * than EL3 488 */ 489 if (is_ctx_pauth_supported()) { 490 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 491 } 492 493 /* 494 * SCR_EL3.PIEN: Enable permission indirection and overlay 495 * registers for AArch64 if present. 496 */ 497 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 498 scr_el3 |= SCR_PIEN_BIT; 499 } 500 501 /* 502 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 503 */ 504 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 505 scr_el3 |= SCR_GCSEn_BIT; 506 } 507 508 /* 509 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 510 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 511 * next mode is Hyp. 512 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 513 * same conditions as HVC instructions and when the processor supports 514 * ARMv8.6-FGT. 515 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 516 * CNTPOFF_EL2 register under the same conditions as HVC instructions 517 * and when the processor supports ECV. 518 */ 519 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 520 || ((GET_RW(ep->spsr) != MODE_RW_64) 521 && (GET_M32(ep->spsr) == MODE32_hyp))) { 522 scr_el3 |= SCR_HCE_BIT; 523 524 if (is_feat_fgt_supported()) { 525 scr_el3 |= SCR_FGTEN_BIT; 526 } 527 528 if (is_feat_ecv_supported()) { 529 scr_el3 |= SCR_ECVEN_BIT; 530 } 531 } 532 533 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 534 if (is_feat_twed_supported()) { 535 /* Set delay in SCR_EL3 */ 536 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 537 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 538 << SCR_TWEDEL_SHIFT); 539 540 /* Enable WFE delay */ 541 scr_el3 |= SCR_TWEDEn_BIT; 542 } 543 544 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 545 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 546 if (is_feat_sel2_supported()) { 547 scr_el3 |= SCR_EEL2_BIT; 548 } 549 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 550 551 if (is_feat_mec_supported()) { 552 scr_el3 |= SCR_MECEn_BIT; 553 } 554 555 /* 556 * Populate EL3 state so that we've the right context 557 * before doing ERET 558 */ 559 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 560 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 561 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 562 563 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 564 mdcr_el3 = MDCR_EL3_RESET_VAL; 565 566 /* --------------------------------------------------------------------- 567 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 568 * Some fields are architecturally UNKNOWN on reset. 569 * 570 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 571 * Debug exceptions, other than Breakpoint Instruction exceptions, are 572 * disabled from all ELs in Secure state. 573 * 574 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 575 * privileged debug from S-EL1. 576 * 577 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 578 * access to the powerdown debug registers do not trap to EL3. 579 * 580 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 581 * debug registers, other than those registers that are controlled by 582 * MDCR_EL3.TDOSA. 583 */ 584 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 585 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 586 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 587 588 #if IMAGE_BL31 589 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 590 if (is_feat_trf_supported()) { 591 trf_enable(ctx); 592 } 593 594 if (is_feat_tcr2_supported()) { 595 tcr2_enable(ctx); 596 } 597 598 pmuv3_enable(ctx); 599 600 #if CTX_INCLUDE_EL2_REGS 601 /* 602 * Initialize SCTLR_EL2 context register with reset value. 603 */ 604 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 605 #endif /* CTX_INCLUDE_EL2_REGS */ 606 #endif /* IMAGE_BL31 */ 607 608 /* 609 * Store the X0-X7 value from the entrypoint into the context 610 * Use memcpy as we are in control of the layout of the structures 611 */ 612 gp_regs = get_gpregs_ctx(ctx); 613 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 614 } 615 616 /******************************************************************************* 617 * Context management library initialization routine. This library is used by 618 * runtime services to share pointers to 'cpu_context' structures for secure 619 * non-secure and realm states. Management of the structures and their associated 620 * memory is not done by the context management library e.g. the PSCI service 621 * manages the cpu context used for entry from and exit to the non-secure state. 622 * The Secure payload dispatcher service manages the context(s) corresponding to 623 * the secure state. It also uses this library to get access to the non-secure 624 * state cpu context pointers. 625 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 626 * which will be used for programming an entry into a lower EL. The same context 627 * will be used to save state upon exception entry from that EL. 628 ******************************************************************************/ 629 void __init cm_init(void) 630 { 631 /* 632 * The context management library has only global data to initialize, but 633 * that will be done when the BSS is zeroed out. 634 */ 635 } 636 637 /******************************************************************************* 638 * This is the high-level function used to initialize the cpu_context 'ctx' for 639 * first use. It performs initializations that are common to all security states 640 * and initializations specific to the security state specified in 'ep' 641 ******************************************************************************/ 642 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 643 { 644 size_t security_state; 645 646 assert(ctx != NULL); 647 648 /* 649 * Perform initializations that are common 650 * to all security states 651 */ 652 setup_context_common(ctx, ep); 653 654 security_state = GET_SECURITY_STATE(ep->h.attr); 655 656 /* Perform security state specific initializations */ 657 switch (security_state) { 658 case SECURE: 659 setup_secure_context(ctx, ep); 660 break; 661 #if ENABLE_RME && IMAGE_BL31 662 case REALM: 663 setup_realm_context(ctx, ep); 664 break; 665 #endif 666 case NON_SECURE: 667 setup_ns_context(ctx, ep); 668 break; 669 default: 670 ERROR("Invalid security state\n"); 671 panic(); 672 break; 673 } 674 } 675 676 /******************************************************************************* 677 * Enable architecture extensions for EL3 execution. This function only updates 678 * registers in-place which are expected to either never change or be 679 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 680 ******************************************************************************/ 681 #if IMAGE_BL31 682 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 683 { 684 if (is_feat_pauth_supported()) { 685 pauth_init_enable_el3(); 686 } 687 688 if (is_feat_sve_supported()) { 689 sve_init_el3(); 690 } 691 692 if (is_feat_amu_supported()) { 693 amu_init_el3(my_idx); 694 } 695 696 if (is_feat_sme_supported()) { 697 sme_init_el3(); 698 } 699 700 if (is_feat_fgwte3_supported()) { 701 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 702 } 703 704 if (is_feat_mpam_supported()) { 705 mpam_init_el3(); 706 } 707 708 if (is_feat_cpa2_supported()) { 709 cpa2_enable_el3(); 710 } 711 712 pmuv3_init_el3(); 713 } 714 715 /****************************************************************************** 716 * Function to initialise the registers with the RESET values in the context 717 * memory, which are maintained per world. 718 ******************************************************************************/ 719 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 720 { 721 /* 722 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 723 * 724 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 725 * by Advanced SIMD, floating-point or SVE instructions (if 726 * implemented) do not trap to EL3. 727 * 728 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 729 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 730 */ 731 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 732 733 per_world_ctx->ctx_cptr_el3 = cptr_el3; 734 735 /* 736 * Initialize MPAM3_EL3 to its default reset value 737 * 738 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 739 * all lower ELn MPAM3_EL3 register access to, trap to EL3 740 */ 741 742 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 743 } 744 745 /******************************************************************************* 746 * Initialise per_world_context for Non-Secure world. 747 * This function enables the architecture extensions, which have same value 748 * across the cores for the non-secure world. 749 ******************************************************************************/ 750 static void manage_extensions_nonsecure_per_world(void) 751 { 752 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 753 754 if (is_feat_sme_supported()) { 755 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 756 } 757 758 if (is_feat_sve_supported()) { 759 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 760 } 761 762 if (is_feat_amu_supported()) { 763 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 764 } 765 766 if (is_feat_sys_reg_trace_supported()) { 767 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 768 } 769 770 if (is_feat_mpam_supported()) { 771 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 772 } 773 774 if (is_feat_fpmr_supported()) { 775 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 776 } 777 } 778 779 /******************************************************************************* 780 * Initialise per_world_context for Secure world. 781 * This function enables the architecture extensions, which have same value 782 * across the cores for the secure world. 783 ******************************************************************************/ 784 static void manage_extensions_secure_per_world(void) 785 { 786 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 787 788 if (is_feat_sme_supported()) { 789 790 if (ENABLE_SME_FOR_SWD) { 791 /* 792 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 793 * SME, SVE, and FPU/SIMD context properly managed. 794 */ 795 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 796 } else { 797 /* 798 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 799 * world can safely use the associated registers. 800 */ 801 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 802 } 803 } 804 if (is_feat_sve_supported()) { 805 if (ENABLE_SVE_FOR_SWD) { 806 /* 807 * Enable SVE and FPU in secure context, SPM must ensure 808 * that the SVE and FPU register contexts are properly managed. 809 */ 810 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 811 } else { 812 /* 813 * Disable SVE and FPU in secure context so non-secure world 814 * can safely use them. 815 */ 816 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 817 } 818 } 819 820 /* NS can access this but Secure shouldn't */ 821 if (is_feat_sys_reg_trace_supported()) { 822 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 823 } 824 } 825 826 static void manage_extensions_realm_per_world(void) 827 { 828 #if ENABLE_RME 829 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 830 831 if (is_feat_sve_supported()) { 832 /* 833 * Enable SVE and FPU in realm context when it is enabled for NS. 834 * Realm manager must ensure that the SVE and FPU register 835 * contexts are properly managed. 836 */ 837 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 838 } 839 840 /* NS can access this but Realm shouldn't */ 841 if (is_feat_sys_reg_trace_supported()) { 842 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 843 } 844 845 /* 846 * If SME/SME2 is supported and enabled for NS world, then disable trapping 847 * of SME instructions for Realm world. RMM will save/restore required 848 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 849 */ 850 if (is_feat_sme_supported()) { 851 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 852 } 853 854 /* 855 * If FEAT_MPAM is supported and enabled, then disable trapping access 856 * to the MPAM registers for Realm world. Instead, RMM will configure 857 * the access to be trapped by itself so it can inject undefined aborts 858 * back to the Realm. 859 */ 860 if (is_feat_mpam_supported()) { 861 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 862 } 863 #endif /* ENABLE_RME */ 864 } 865 866 void cm_manage_extensions_per_world(void) 867 { 868 manage_extensions_nonsecure_per_world(); 869 manage_extensions_secure_per_world(); 870 manage_extensions_realm_per_world(); 871 } 872 #endif /* IMAGE_BL31 */ 873 874 /******************************************************************************* 875 * Enable architecture extensions on first entry to Non-secure world. 876 ******************************************************************************/ 877 static void manage_extensions_nonsecure(cpu_context_t *ctx) 878 { 879 #if IMAGE_BL31 880 /* NOTE: registers are not context switched */ 881 if (is_feat_amu_supported()) { 882 amu_enable(ctx); 883 } 884 885 if (is_feat_sme_supported()) { 886 sme_enable(ctx); 887 } 888 889 if (is_feat_fgt2_supported()) { 890 fgt2_enable(ctx); 891 } 892 893 if (is_feat_debugv8p9_supported()) { 894 debugv8p9_extended_bp_wp_enable(ctx); 895 } 896 897 if (is_feat_spe_supported()) { 898 spe_enable_ns(ctx); 899 } 900 901 if (is_feat_trbe_supported()) { 902 if (check_if_trbe_disable_affected_core()) { 903 trbe_disable_ns(ctx); 904 } else { 905 trbe_enable_ns(ctx); 906 } 907 } 908 909 if (is_feat_brbe_supported()) { 910 brbe_enable(ctx); 911 } 912 #endif /* IMAGE_BL31 */ 913 } 914 915 #if INIT_UNUSED_NS_EL2 916 /******************************************************************************* 917 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 918 * world when EL2 is empty and unused. 919 ******************************************************************************/ 920 static void manage_extensions_nonsecure_el2_unused(void) 921 { 922 #if IMAGE_BL31 923 if (is_feat_spe_supported()) { 924 spe_init_el2_unused(); 925 } 926 927 if (is_feat_amu_supported()) { 928 amu_init_el2_unused(); 929 } 930 931 if (is_feat_mpam_supported()) { 932 mpam_init_el2_unused(); 933 } 934 935 if (is_feat_trbe_supported()) { 936 trbe_init_el2_unused(); 937 } 938 939 if (is_feat_sys_reg_trace_supported()) { 940 sys_reg_trace_init_el2_unused(); 941 } 942 943 if (is_feat_trf_supported()) { 944 trf_init_el2_unused(); 945 } 946 947 pmuv3_init_el2_unused(); 948 949 if (is_feat_sve_supported()) { 950 sve_init_el2_unused(); 951 } 952 953 if (is_feat_sme_supported()) { 954 sme_init_el2_unused(); 955 } 956 957 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 958 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 959 } 960 961 if (is_feat_pauth_supported()) { 962 pauth_enable_el2(); 963 } 964 #endif /* IMAGE_BL31 */ 965 } 966 #endif /* INIT_UNUSED_NS_EL2 */ 967 968 /******************************************************************************* 969 * Enable architecture extensions on first entry to Secure world. 970 ******************************************************************************/ 971 static void manage_extensions_secure(cpu_context_t *ctx) 972 { 973 #if IMAGE_BL31 974 if (is_feat_sme_supported()) { 975 if (ENABLE_SME_FOR_SWD) { 976 /* 977 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 978 * must ensure SME, SVE, and FPU/SIMD context properly managed. 979 */ 980 sme_init_el3(); 981 sme_enable(ctx); 982 } else { 983 /* 984 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 985 * world can safely use the associated registers. 986 */ 987 sme_disable(ctx); 988 } 989 } 990 991 if (is_feat_spe_supported()) { 992 spe_disable_secure(ctx); 993 } 994 995 if (is_feat_trbe_supported()) { 996 trbe_disable_secure(ctx); 997 } 998 #endif /* IMAGE_BL31 */ 999 } 1000 1001 /******************************************************************************* 1002 * The following function initializes the cpu_context for the current CPU 1003 * for first use, and sets the initial entrypoint state as specified by the 1004 * entry_point_info structure. 1005 ******************************************************************************/ 1006 void cm_init_my_context(const entry_point_info_t *ep) 1007 { 1008 cpu_context_t *ctx; 1009 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1010 cm_setup_context(ctx, ep); 1011 } 1012 1013 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1014 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1015 { 1016 #if INIT_UNUSED_NS_EL2 1017 u_register_t hcr_el2 = HCR_RESET_VAL; 1018 u_register_t mdcr_el2; 1019 u_register_t scr_el3; 1020 1021 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1022 1023 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1024 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1025 hcr_el2 |= HCR_RW_BIT; 1026 } 1027 1028 write_hcr_el2(hcr_el2); 1029 1030 /* 1031 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1032 * All fields have architecturally UNKNOWN reset values. 1033 */ 1034 write_cptr_el2(CPTR_EL2_RESET_VAL); 1035 1036 /* 1037 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1038 * reset and are set to zero except for field(s) listed below. 1039 * 1040 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1041 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1042 * 1043 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1044 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1045 */ 1046 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1047 1048 /* 1049 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1050 * UNKNOWN value. 1051 */ 1052 write_cntvoff_el2(0); 1053 1054 /* 1055 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1056 * respectively. 1057 */ 1058 write_vpidr_el2(read_midr_el1()); 1059 write_vmpidr_el2(read_mpidr_el1()); 1060 1061 /* 1062 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1063 * 1064 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1065 * translation is disabled, cache maintenance operations depend on the 1066 * VMID. 1067 * 1068 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1069 * disabled. 1070 */ 1071 write_vttbr_el2(VTTBR_RESET_VAL & 1072 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1073 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1074 1075 /* 1076 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1077 * Some fields are architecturally UNKNOWN on reset. 1078 * 1079 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1080 * register accesses to the Debug ROM registers are not trapped to EL2. 1081 * 1082 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1083 * accesses to the powerdown debug registers are not trapped to EL2. 1084 * 1085 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1086 * debug registers do not trap to EL2. 1087 * 1088 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1089 * EL2. 1090 */ 1091 mdcr_el2 = MDCR_EL2_RESET_VAL & 1092 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1093 MDCR_EL2_TDE_BIT); 1094 1095 write_mdcr_el2(mdcr_el2); 1096 1097 /* 1098 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1099 * 1100 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1101 * EL1 accesses to System registers do not trap to EL2. 1102 */ 1103 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1104 1105 /* 1106 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1107 * reset. 1108 * 1109 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1110 * and prevent timer interrupts. 1111 */ 1112 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1113 1114 manage_extensions_nonsecure_el2_unused(); 1115 #endif /* INIT_UNUSED_NS_EL2 */ 1116 } 1117 1118 /******************************************************************************* 1119 * Prepare the CPU system registers for first entry into realm, secure, or 1120 * normal world. 1121 * 1122 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1123 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1124 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1125 * For all entries, the EL1 registers are initialized from the cpu_context 1126 ******************************************************************************/ 1127 void cm_prepare_el3_exit(size_t security_state) 1128 { 1129 u_register_t sctlr_el2, scr_el3; 1130 cpu_context_t *ctx = cm_get_context(security_state); 1131 1132 assert(ctx != NULL); 1133 1134 if (security_state == NON_SECURE) { 1135 uint64_t el2_implemented = el_implemented(2); 1136 1137 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1138 CTX_SCR_EL3); 1139 1140 if (el2_implemented != EL_IMPL_NONE) { 1141 1142 /* 1143 * If context is not being used for EL2, initialize 1144 * HCRX_EL2 with its init value here. 1145 */ 1146 if (is_feat_hcx_supported()) { 1147 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1148 } 1149 1150 /* 1151 * Initialize Fine-grained trap registers introduced 1152 * by FEAT_FGT so all traps are initially disabled when 1153 * switching to EL2 or a lower EL, preventing undesired 1154 * behavior. 1155 */ 1156 if (is_feat_fgt_supported()) { 1157 /* 1158 * Initialize HFG*_EL2 registers with a default 1159 * value so legacy systems unaware of FEAT_FGT 1160 * do not get trapped due to their lack of 1161 * initialization for this feature. 1162 */ 1163 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1164 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1165 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1166 } 1167 1168 /* Condition to ensure EL2 is being used. */ 1169 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1170 /* Initialize SCTLR_EL2 register with reset value. */ 1171 sctlr_el2 = SCTLR_EL2_RES1; 1172 1173 /* 1174 * If workaround of errata 764081 for Cortex-A75 1175 * is used then set SCTLR_EL2.IESB to enable 1176 * Implicit Error Synchronization Barrier. 1177 */ 1178 if (errata_a75_764081_applies()) { 1179 sctlr_el2 |= SCTLR_IESB_BIT; 1180 } 1181 1182 write_sctlr_el2(sctlr_el2); 1183 } else { 1184 /* 1185 * (scr_el3 & SCR_HCE_BIT==0) 1186 * EL2 implemented but unused. 1187 */ 1188 init_nonsecure_el2_unused(ctx); 1189 } 1190 } 1191 1192 if (is_feat_fgwte3_supported()) { 1193 /* 1194 * TCR_EL3 and ACTLR_EL3 could be overwritten 1195 * by platforms and hence is locked a bit late. 1196 */ 1197 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1198 } 1199 } 1200 #if (!CTX_INCLUDE_EL2_REGS) 1201 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1202 cm_el1_sysregs_context_restore(security_state); 1203 #endif 1204 cm_set_next_eret_context(security_state); 1205 } 1206 1207 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1208 1209 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1210 { 1211 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1212 if (is_feat_amu_supported()) { 1213 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1214 } 1215 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1216 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1217 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1218 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1219 } 1220 1221 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1222 { 1223 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1224 if (is_feat_amu_supported()) { 1225 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1226 } 1227 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1228 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1229 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1230 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1231 } 1232 1233 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1234 { 1235 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1236 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1237 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1238 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1239 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1240 } 1241 1242 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1243 { 1244 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1245 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1246 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1247 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1248 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1249 } 1250 1251 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1252 { 1253 u_register_t mpam_idr = read_mpamidr_el1(); 1254 1255 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1256 1257 /* 1258 * The context registers that we intend to save would be part of the 1259 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1260 */ 1261 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1262 return; 1263 } 1264 1265 /* 1266 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1267 * MPAMIDR_HAS_HCR_BIT == 1. 1268 */ 1269 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1270 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1271 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1272 1273 /* 1274 * The number of MPAMVPM registers is implementation defined, their 1275 * number is stored in the MPAMIDR_EL1 register. 1276 */ 1277 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1278 case 7: 1279 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1280 __fallthrough; 1281 case 6: 1282 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1283 __fallthrough; 1284 case 5: 1285 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1286 __fallthrough; 1287 case 4: 1288 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1289 __fallthrough; 1290 case 3: 1291 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1292 __fallthrough; 1293 case 2: 1294 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1295 __fallthrough; 1296 case 1: 1297 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1298 break; 1299 } 1300 } 1301 1302 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1303 { 1304 u_register_t mpam_idr = read_mpamidr_el1(); 1305 1306 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1307 1308 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1309 return; 1310 } 1311 1312 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1313 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1314 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1315 1316 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1317 case 7: 1318 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1319 __fallthrough; 1320 case 6: 1321 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1322 __fallthrough; 1323 case 5: 1324 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1325 __fallthrough; 1326 case 4: 1327 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1328 __fallthrough; 1329 case 3: 1330 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1331 __fallthrough; 1332 case 2: 1333 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1334 __fallthrough; 1335 case 1: 1336 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1337 break; 1338 } 1339 } 1340 1341 /* --------------------------------------------------------------------------- 1342 * The following registers are not added: 1343 * ICH_AP0R<n>_EL2 1344 * ICH_AP1R<n>_EL2 1345 * ICH_LR<n>_EL2 1346 * 1347 * NOTE: For a system with S-EL2 present but not enabled, accessing 1348 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1349 * SCR_EL3.NS = 1 before accessing this register. 1350 * --------------------------------------------------------------------------- 1351 */ 1352 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1353 { 1354 u_register_t scr_el3 = read_scr_el3(); 1355 1356 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1357 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1358 #else 1359 write_scr_el3(scr_el3 | SCR_NS_BIT); 1360 isb(); 1361 1362 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1363 1364 write_scr_el3(scr_el3); 1365 isb(); 1366 #endif 1367 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1368 1369 if (errata_ich_vmcr_el2_applies()) { 1370 if (security_state == SECURE) { 1371 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1372 } else { 1373 write_scr_el3(scr_el3 | SCR_NS_BIT); 1374 } 1375 isb(); 1376 } 1377 1378 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1379 1380 if (errata_ich_vmcr_el2_applies()) { 1381 write_scr_el3(scr_el3); 1382 isb(); 1383 } 1384 } 1385 1386 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1387 { 1388 u_register_t scr_el3 = read_scr_el3(); 1389 1390 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1391 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1392 #else 1393 write_scr_el3(scr_el3 | SCR_NS_BIT); 1394 isb(); 1395 1396 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1397 1398 write_scr_el3(scr_el3); 1399 isb(); 1400 #endif 1401 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1402 1403 if (errata_ich_vmcr_el2_applies()) { 1404 if (security_state == SECURE) { 1405 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1406 } else { 1407 write_scr_el3(scr_el3 | SCR_NS_BIT); 1408 } 1409 isb(); 1410 } 1411 1412 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1413 1414 if (errata_ich_vmcr_el2_applies()) { 1415 write_scr_el3(scr_el3); 1416 isb(); 1417 } 1418 } 1419 1420 /* ----------------------------------------------------- 1421 * The following registers are not added: 1422 * AMEVCNTVOFF0<n>_EL2 1423 * AMEVCNTVOFF1<n>_EL2 1424 * ----------------------------------------------------- 1425 */ 1426 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1427 { 1428 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1429 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1430 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1431 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1432 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1433 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1434 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1435 if (CTX_INCLUDE_AARCH32_REGS) { 1436 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1437 } 1438 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1439 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1440 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1441 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1442 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1443 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1444 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1445 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1446 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1447 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1448 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1449 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1450 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1451 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1452 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1453 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1454 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1455 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1456 1457 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1458 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1459 } 1460 1461 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1462 { 1463 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1464 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1465 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1466 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1467 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1468 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1469 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1470 if (CTX_INCLUDE_AARCH32_REGS) { 1471 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1472 } 1473 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1474 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1475 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1476 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1477 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1478 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1479 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1480 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1481 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1482 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1483 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1484 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1485 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1486 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1487 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1488 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1489 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1490 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1491 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1492 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1493 } 1494 1495 /******************************************************************************* 1496 * Save EL2 sysreg context 1497 ******************************************************************************/ 1498 void cm_el2_sysregs_context_save(uint32_t security_state) 1499 { 1500 cpu_context_t *ctx; 1501 el2_sysregs_t *el2_sysregs_ctx; 1502 1503 ctx = cm_get_context(security_state); 1504 assert(ctx != NULL); 1505 1506 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1507 1508 el2_sysregs_context_save_common(el2_sysregs_ctx); 1509 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1510 1511 if (is_feat_mte2_supported()) { 1512 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1513 } 1514 1515 if (is_feat_mpam_supported()) { 1516 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1517 } 1518 1519 if (is_feat_fgt_supported()) { 1520 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1521 } 1522 1523 if (is_feat_fgt2_supported()) { 1524 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1525 } 1526 1527 if (is_feat_ecv_v2_supported()) { 1528 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1529 } 1530 1531 if (is_feat_vhe_supported()) { 1532 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1533 read_contextidr_el2()); 1534 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1535 } 1536 1537 if (is_feat_ras_supported()) { 1538 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1539 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1540 } 1541 1542 if (is_feat_nv2_supported()) { 1543 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1544 } 1545 1546 if (is_feat_trf_supported()) { 1547 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1548 } 1549 1550 if (is_feat_csv2_2_supported()) { 1551 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1552 read_scxtnum_el2()); 1553 } 1554 1555 if (is_feat_hcx_supported()) { 1556 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1557 } 1558 1559 if (is_feat_tcr2_supported()) { 1560 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1561 } 1562 1563 if (is_feat_sxpie_supported()) { 1564 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1565 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1566 } 1567 1568 if (is_feat_sxpoe_supported()) { 1569 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1570 } 1571 1572 if (is_feat_brbe_supported()) { 1573 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1574 } 1575 1576 if (is_feat_s2pie_supported()) { 1577 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1578 } 1579 1580 if (is_feat_gcs_supported()) { 1581 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1582 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1583 } 1584 1585 if (is_feat_sctlr2_supported()) { 1586 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1587 } 1588 } 1589 1590 /******************************************************************************* 1591 * Restore EL2 sysreg context 1592 ******************************************************************************/ 1593 void cm_el2_sysregs_context_restore(uint32_t security_state) 1594 { 1595 cpu_context_t *ctx; 1596 el2_sysregs_t *el2_sysregs_ctx; 1597 1598 ctx = cm_get_context(security_state); 1599 assert(ctx != NULL); 1600 1601 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1602 1603 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1604 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1605 1606 if (is_feat_mte2_supported()) { 1607 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1608 } 1609 1610 if (is_feat_mpam_supported()) { 1611 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1612 } 1613 1614 if (is_feat_fgt_supported()) { 1615 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1616 } 1617 1618 if (is_feat_fgt2_supported()) { 1619 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1620 } 1621 1622 if (is_feat_ecv_v2_supported()) { 1623 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1624 } 1625 1626 if (is_feat_vhe_supported()) { 1627 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1628 contextidr_el2)); 1629 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1630 } 1631 1632 if (is_feat_ras_supported()) { 1633 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1634 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1635 } 1636 1637 if (is_feat_nv2_supported()) { 1638 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1639 } 1640 1641 if (is_feat_trf_supported()) { 1642 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1643 } 1644 1645 if (is_feat_csv2_2_supported()) { 1646 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1647 scxtnum_el2)); 1648 } 1649 1650 if (is_feat_hcx_supported()) { 1651 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1652 } 1653 1654 if (is_feat_tcr2_supported()) { 1655 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1656 } 1657 1658 if (is_feat_sxpie_supported()) { 1659 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1660 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1661 } 1662 1663 if (is_feat_sxpoe_supported()) { 1664 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1665 } 1666 1667 if (is_feat_s2pie_supported()) { 1668 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1669 } 1670 1671 if (is_feat_gcs_supported()) { 1672 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1673 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1674 } 1675 1676 if (is_feat_sctlr2_supported()) { 1677 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1678 } 1679 1680 if (is_feat_brbe_supported()) { 1681 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1682 } 1683 } 1684 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1685 1686 /******************************************************************************* 1687 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1688 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1689 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1690 * cm_prepare_el3_exit function. 1691 ******************************************************************************/ 1692 void cm_prepare_el3_exit_ns(void) 1693 { 1694 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1695 #if ENABLE_ASSERTIONS 1696 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1697 assert(ctx != NULL); 1698 1699 /* Assert that EL2 is used. */ 1700 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1701 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1702 (el_implemented(2U) != EL_IMPL_NONE)); 1703 #endif /* ENABLE_ASSERTIONS */ 1704 1705 /* Restore EL2 sysreg contexts */ 1706 cm_el2_sysregs_context_restore(NON_SECURE); 1707 cm_set_next_eret_context(NON_SECURE); 1708 #else 1709 cm_prepare_el3_exit(NON_SECURE); 1710 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1711 } 1712 1713 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1714 /******************************************************************************* 1715 * The next set of six functions are used by runtime services to save and restore 1716 * EL1 context on the 'cpu_context' structure for the specified security state. 1717 ******************************************************************************/ 1718 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1719 { 1720 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1721 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1722 1723 #if (!ERRATA_SPECULATIVE_AT) 1724 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1725 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1726 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1727 1728 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1729 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1730 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1731 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1732 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1733 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1734 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1735 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1736 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1737 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1738 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1739 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1740 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1741 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1742 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1743 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1744 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1745 1746 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1747 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1748 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1749 1750 if (CTX_INCLUDE_AARCH32_REGS) { 1751 /* Save Aarch32 registers */ 1752 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1753 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1754 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1755 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1756 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1757 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1758 } 1759 1760 /* Save counter-timer kernel control register */ 1761 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1762 #if NS_TIMER_SWITCH 1763 /* Save NS Timer registers */ 1764 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1765 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1766 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1767 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1768 #endif 1769 1770 if (is_feat_mte2_supported()) { 1771 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1772 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1773 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1774 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1775 } 1776 1777 if (is_feat_ras_supported()) { 1778 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1779 } 1780 1781 if (is_feat_s1pie_supported()) { 1782 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1783 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1784 } 1785 1786 if (is_feat_s1poe_supported()) { 1787 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1788 } 1789 1790 if (is_feat_s2poe_supported()) { 1791 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1792 } 1793 1794 if (is_feat_tcr2_supported()) { 1795 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1796 } 1797 1798 if (is_feat_trf_supported()) { 1799 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1800 } 1801 1802 if (is_feat_csv2_2_supported()) { 1803 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1804 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1805 } 1806 1807 if (is_feat_gcs_supported()) { 1808 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1809 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1810 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1811 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1812 } 1813 1814 if (is_feat_the_supported()) { 1815 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1816 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1817 } 1818 1819 if (is_feat_sctlr2_supported()) { 1820 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1821 } 1822 1823 if (is_feat_ls64_accdata_supported()) { 1824 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1825 } 1826 } 1827 1828 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1829 { 1830 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1831 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1832 1833 #if (!ERRATA_SPECULATIVE_AT) 1834 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1835 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1836 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1837 1838 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1839 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1840 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1841 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1842 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1843 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1844 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1845 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1846 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1847 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1848 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1849 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1850 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1851 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1852 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1853 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1854 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1855 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1856 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1857 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1858 1859 if (CTX_INCLUDE_AARCH32_REGS) { 1860 /* Restore Aarch32 registers */ 1861 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1862 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1863 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1864 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1865 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1866 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1867 } 1868 1869 /* Restore counter-timer kernel control register */ 1870 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1871 #if NS_TIMER_SWITCH 1872 /* Restore NS Timer registers */ 1873 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1874 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1875 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1876 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1877 #endif 1878 1879 if (is_feat_mte2_supported()) { 1880 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1881 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1882 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1883 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1884 } 1885 1886 if (is_feat_ras_supported()) { 1887 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1888 } 1889 1890 if (is_feat_s1pie_supported()) { 1891 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1892 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1893 } 1894 1895 if (is_feat_s1poe_supported()) { 1896 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1897 } 1898 1899 if (is_feat_s2poe_supported()) { 1900 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1901 } 1902 1903 if (is_feat_tcr2_supported()) { 1904 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1905 } 1906 1907 if (is_feat_trf_supported()) { 1908 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1909 } 1910 1911 if (is_feat_csv2_2_supported()) { 1912 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1913 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1914 } 1915 1916 if (is_feat_gcs_supported()) { 1917 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1918 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1919 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1920 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1921 } 1922 1923 if (is_feat_the_supported()) { 1924 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1925 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1926 } 1927 1928 if (is_feat_sctlr2_supported()) { 1929 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1930 } 1931 1932 if (is_feat_ls64_accdata_supported()) { 1933 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1934 } 1935 } 1936 1937 /******************************************************************************* 1938 * The next couple of functions are used by runtime services to save and restore 1939 * EL1 context on the 'cpu_context' structure for the specified security state. 1940 ******************************************************************************/ 1941 void cm_el1_sysregs_context_save(uint32_t security_state) 1942 { 1943 cpu_context_t *ctx; 1944 1945 ctx = cm_get_context(security_state); 1946 assert(ctx != NULL); 1947 1948 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1949 1950 #if IMAGE_BL31 1951 if (security_state == SECURE) { 1952 PUBLISH_EVENT(cm_exited_secure_world); 1953 } else { 1954 PUBLISH_EVENT(cm_exited_normal_world); 1955 } 1956 #endif 1957 } 1958 1959 void cm_el1_sysregs_context_restore(uint32_t security_state) 1960 { 1961 cpu_context_t *ctx; 1962 1963 ctx = cm_get_context(security_state); 1964 assert(ctx != NULL); 1965 1966 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1967 1968 #if IMAGE_BL31 1969 if (security_state == SECURE) { 1970 PUBLISH_EVENT(cm_entering_secure_world); 1971 } else { 1972 PUBLISH_EVENT(cm_entering_normal_world); 1973 } 1974 #endif 1975 } 1976 1977 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1978 1979 /******************************************************************************* 1980 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1981 * given security state with the given entrypoint 1982 ******************************************************************************/ 1983 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1984 { 1985 cpu_context_t *ctx; 1986 el3_state_t *state; 1987 1988 ctx = cm_get_context(security_state); 1989 assert(ctx != NULL); 1990 1991 /* Populate EL3 state so that ERET jumps to the correct entry */ 1992 state = get_el3state_ctx(ctx); 1993 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1994 } 1995 1996 /******************************************************************************* 1997 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1998 * pertaining to the given security state 1999 ******************************************************************************/ 2000 void cm_set_elr_spsr_el3(uint32_t security_state, 2001 uintptr_t entrypoint, uint32_t spsr) 2002 { 2003 cpu_context_t *ctx; 2004 el3_state_t *state; 2005 2006 ctx = cm_get_context(security_state); 2007 assert(ctx != NULL); 2008 2009 /* Populate EL3 state so that ERET jumps to the correct entry */ 2010 state = get_el3state_ctx(ctx); 2011 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2012 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2013 } 2014 2015 /******************************************************************************* 2016 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2017 * pertaining to the given security state using the value and bit position 2018 * specified in the parameters. It preserves all other bits. 2019 ******************************************************************************/ 2020 void cm_write_scr_el3_bit(uint32_t security_state, 2021 uint32_t bit_pos, 2022 uint32_t value) 2023 { 2024 cpu_context_t *ctx; 2025 el3_state_t *state; 2026 u_register_t scr_el3; 2027 2028 ctx = cm_get_context(security_state); 2029 assert(ctx != NULL); 2030 2031 /* Ensure that the bit position is a valid one */ 2032 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2033 2034 /* Ensure that the 'value' is only a bit wide */ 2035 assert(value <= 1U); 2036 2037 /* 2038 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2039 * and set it to its new value. 2040 */ 2041 state = get_el3state_ctx(ctx); 2042 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2043 scr_el3 &= ~(1UL << bit_pos); 2044 scr_el3 |= (u_register_t)value << bit_pos; 2045 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2046 } 2047 2048 /******************************************************************************* 2049 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2050 * given security state. 2051 ******************************************************************************/ 2052 u_register_t cm_get_scr_el3(uint32_t security_state) 2053 { 2054 const cpu_context_t *ctx; 2055 const el3_state_t *state; 2056 2057 ctx = cm_get_context(security_state); 2058 assert(ctx != NULL); 2059 2060 /* Populate EL3 state so that ERET jumps to the correct entry */ 2061 state = get_el3state_ctx(ctx); 2062 return read_ctx_reg(state, CTX_SCR_EL3); 2063 } 2064 2065 /******************************************************************************* 2066 * This function is used to program the context that's used for exception 2067 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2068 * the required security state 2069 ******************************************************************************/ 2070 void cm_set_next_eret_context(uint32_t security_state) 2071 { 2072 cpu_context_t *ctx; 2073 2074 ctx = cm_get_context(security_state); 2075 assert(ctx != NULL); 2076 2077 cm_set_next_context(ctx); 2078 } 2079