1 /* 2 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/css/css_mhu_doorbell.h> 16 #include <drivers/arm/css/scmi.h> 17 #include <drivers/arm/dsu.h> 18 #include <drivers/arm/sbsa.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <plat/arm/common/plat_arm.h> 22 #include <plat/common/platform.h> 23 24 #ifdef PLATFORM_TEST_TFM_TESTSUITE 25 #include <psa/crypto_platform.h> 26 #include <psa/crypto_types.h> 27 #include <psa/crypto_values.h> 28 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 29 #include <psa/error.h> 30 31 #include <plat/common/platform.h> 32 #include <tc_rse_comms.h> 33 34 #ifdef PLATFORM_TEST_TFM_TESTSUITE 35 /* 36 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 37 * mbedTLS config option) so we need to provide an implementation of 38 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 39 * actually use any of external RNG and this function is only needed during 40 * the execution of TF-M testsuite during exporting the public part of the 41 * delegated attestation key. 42 */ 43 psa_status_t mbedtls_psa_external_get_random( 44 mbedtls_psa_external_random_context_t *context, 45 uint8_t *output, size_t output_size, 46 size_t *output_length) 47 { 48 for (size_t i = 0U; i < output_size; i++) { 49 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 50 } 51 52 *output_length = output_size; 53 54 return PSA_SUCCESS; 55 } 56 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 57 58 static scmi_channel_plat_info_t tc_scmi_plat_info = { 59 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 60 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 61 .db_preserve_mask = 0xfffffffe, 62 .db_modify_mask = 0x1, 63 .ring_doorbell = &mhu_ring_doorbell, 64 }; 65 66 /* the bottom 3 AMU group 1 counters */ 67 #define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2)) 68 69 uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT] = { 70 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 71 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 72 #if PLATFORM_CORE_COUNT == 14 73 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 74 MPMM_GEARS, MPMM_GEARS 75 #endif 76 }; 77 78 const dsu_driver_data_t plat_dsu_data = { 79 .clusterpwrdwn_pwrdn = false, 80 .clusterpwrdwn_memret = false, 81 .clusterpwrctlr_cachepwr = CLUSTERPWRCTLR_CACHEPWR_RESET, 82 .clusterpwrctlr_funcret = CLUSTERPWRCTLR_FUNCRET_RESET 83 }; 84 85 #if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) 86 static void enable_ns_mcn_pmu(void) 87 { 88 /* 89 * Enable non-secure access to MCN PMU registers 90 */ 91 for (int i = 0; i < MCN_INSTANCES; i++) { 92 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) + 93 MCN_SCR_OFFSET; 94 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); 95 } 96 } 97 #endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ 98 99 #if TARGET_PLATFORM == 3 100 static void set_mcn_slc_alloc_mode(void) 101 { 102 /* 103 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to 104 * 0b01 (always alloc), configure both to 0b10 (use bus signal 105 * attribute from interface). 106 */ 107 for (int i = 0; i < MCN_INSTANCES; i++) { 108 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) + 109 MPAM_SLCCFG_CTL_OFFSET; 110 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) + 111 MPAM_SLCCFG_CTL_OFFSET; 112 113 mmio_clrsetbits_32(slccfg_ctl_ns, 114 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 115 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 116 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 117 mmio_clrsetbits_32(slccfg_ctl_s, 118 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 119 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 120 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 121 } 122 } 123 #endif 124 125 void bl31_platform_setup(void) 126 { 127 psa_status_t status; 128 129 tc_bl31_common_platform_setup(); 130 #if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) 131 enable_ns_mcn_pmu(); 132 #endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ 133 #if TARGET_PLATFORM == 3 134 set_mcn_slc_alloc_mode(); 135 plat_arm_ni_setup(NCI_BASE_ADDR); 136 #endif 137 138 /* Initialise RSE communication channel */ 139 status = plat_rse_comms_init(); 140 if (status != PSA_SUCCESS) { 141 ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status); 142 } 143 } 144 145 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 146 { 147 148 return &tc_scmi_plat_info; 149 150 } 151 152 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 153 u_register_t arg2, u_register_t arg3) 154 { 155 /* Initialize the console to provide early debug support */ 156 arm_console_boot_init(); 157 158 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 159 160 #if !TRANSFER_LIST 161 /* Fill the properties struct with the info from the config dtb */ 162 fconf_populate("FW_CONFIG", arg1); 163 #endif 164 } 165 166 #ifdef PLATFORM_TESTS 167 static __dead2 void tc_run_platform_tests(void) 168 { 169 int tests_failed; 170 171 printf("\nStarting platform tests...\n"); 172 173 #ifdef PLATFORM_TEST_NV_COUNTERS 174 tests_failed = nv_counter_test(); 175 #elif PLATFORM_TEST_ROTPK 176 tests_failed = rotpk_test(); 177 #elif PLATFORM_TEST_TFM_TESTSUITE 178 tests_failed = run_platform_tests(); 179 #endif 180 181 printf("Platform tests %s.\n", 182 (tests_failed != 0) ? "failed" : "succeeded"); 183 184 /* Suspend booting, no matter the tests outcome. */ 185 printf("Suspend booting...\n"); 186 plat_error_handler(-1); 187 } 188 #endif 189 190 void tc_bl31_common_platform_setup(void) 191 { 192 arm_bl31_platform_setup(); 193 194 #ifdef PLATFORM_TESTS 195 tc_run_platform_tests(); 196 #endif 197 } 198 199 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 200 { 201 return css_scmi_override_pm_ops(ops); 202 } 203 204 void __init bl31_plat_arch_setup(void) 205 { 206 arm_bl31_plat_arch_setup(); 207 208 /* 209 * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List 210 * as an entry with the tag TL_TAG_FDT. In this case, the configuration 211 * is already available, so the fconf_populate mechanism is not needed. 212 * The code block below is only required when TRANSFER_LIST is not used. 213 */ 214 #if !TRANSFER_LIST 215 /* HW_CONFIG was also loaded by BL2 */ 216 const struct dyn_cfg_dtb_info_t *hw_config_info; 217 218 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 219 assert(hw_config_info != NULL); 220 221 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 222 #endif 223 } 224 225 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 226 void tc_bl31_plat_runtime_setup(void) 227 { 228 /* Start secure watchdog timer. */ 229 plat_arm_secure_wdt_start(); 230 231 arm_bl31_plat_runtime_setup(); 232 } 233 234 void bl31_plat_runtime_setup(void) 235 { 236 tc_bl31_plat_runtime_setup(); 237 } 238 239 /* 240 * Platform handler for Group0 secure interrupt. 241 */ 242 int plat_spmd_handle_group0_interrupt(uint32_t intid) 243 { 244 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 245 if (intid == SBSA_SECURE_WDOG_INTID) { 246 /* Refresh the timer. */ 247 plat_arm_secure_wdt_refresh(); 248 249 return 0; 250 } 251 252 return -1; 253 } 254 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 255