1# 2# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4# Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5# 6# SPDX-License-Identifier: BSD-3-Clause 7# 8 9PLAT_INCLUDES := \ 10 -Iplat/intel/soc/stratix10/include/ \ 11 -Iplat/intel/soc/common/drivers/ \ 12 -Iplat/intel/soc/common/include/ 13 14# Include GICv2 driver files 15include drivers/arm/gic/v2/gicv2.mk 16AGX_GICv2_SOURCES := \ 17 ${GICV2_SOURCES} \ 18 plat/common/plat_gicv2.c 19 20 21PLAT_BL_COMMON_SOURCES := \ 22 ${AGX_GICv2_SOURCES} \ 23 drivers/delay_timer/delay_timer.c \ 24 drivers/delay_timer/generic_delay_timer.c \ 25 drivers/ti/uart/aarch64/16550_console.S \ 26 lib/xlat_tables/aarch64/xlat_tables.c \ 27 lib/xlat_tables/xlat_tables_common.c \ 28 plat/intel/soc/common/aarch64/platform_common.c \ 29 plat/intel/soc/common/aarch64/plat_helpers.S \ 30 plat/intel/soc/common/drivers/ccu/ncore_ccu.c \ 31 plat/intel/soc/common/lib/utils/alignment_utils.c \ 32 plat/intel/soc/common/socfpga_delay_timer.c \ 33 plat/intel/soc/common/soc/socfpga_firewall.c 34 35BL2_SOURCES += \ 36 common/desc_image_load.c \ 37 drivers/mmc/mmc.c \ 38 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ 39 drivers/io/io_storage.c \ 40 drivers/io/io_block.c \ 41 drivers/io/io_fip.c \ 42 drivers/partition/partition.c \ 43 drivers/partition/gpt.c \ 44 drivers/synopsys/emmc/dw_mmc.c \ 45 lib/cpus/aarch64/cortex_a53.S \ 46 plat/intel/soc/stratix10/bl2_plat_setup.c \ 47 plat/intel/soc/stratix10/soc/s10_clock_manager.c \ 48 plat/intel/soc/stratix10/soc/s10_memory_controller.c \ 49 plat/intel/soc/stratix10/soc/s10_mmc.c \ 50 plat/intel/soc/stratix10/soc/s10_pinmux.c \ 51 plat/intel/soc/common/bl2_plat_mem_params_desc.c \ 52 plat/intel/soc/common/socfpga_image_load.c \ 53 plat/intel/soc/common/socfpga_storage.c \ 54 plat/intel/soc/common/soc/socfpga_emac.c \ 55 plat/intel/soc/common/soc/socfpga_handoff.c \ 56 plat/intel/soc/common/soc/socfpga_mailbox.c \ 57 plat/intel/soc/common/soc/socfpga_reset_manager.c \ 58 plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ 59 plat/intel/soc/common/drivers/ddr/ddr.c \ 60 plat/intel/soc/common/drivers/wdt/watchdog.c 61 62include lib/zlib/zlib.mk 63PLAT_INCLUDES += -Ilib/zlib 64BL2_SOURCES += $(ZLIB_SOURCES) 65 66BL31_SOURCES += \ 67 drivers/arm/cci/cci.c \ 68 lib/cpus/aarch64/aem_generic.S \ 69 lib/cpus/aarch64/cortex_a53.S \ 70 plat/common/plat_psci_common.c \ 71 plat/intel/soc/stratix10/soc/s10_clock_manager.c \ 72 plat/intel/soc/stratix10/bl31_plat_setup.c \ 73 plat/intel/soc/common/socfpga_psci.c \ 74 plat/intel/soc/common/socfpga_sip_svc.c \ 75 plat/intel/soc/common/socfpga_sip_svc_v2.c \ 76 plat/intel/soc/common/socfpga_topology.c \ 77 plat/intel/soc/common/sip/socfpga_sip_ecc.c \ 78 plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 79 plat/intel/soc/common/soc/socfpga_mailbox.c \ 80 plat/intel/soc/common/soc/socfpga_reset_manager.c 81 82# Don't have the Linux kernel as a BL33 image by default 83ARM_LINUX_KERNEL_AS_BL33 := 0 84$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) 85$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) 86$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) 87 88# Configs for Boot Source 89SOCFPGA_BOOT_SOURCE_SDMMC ?= 0 90SOCFPGA_BOOT_SOURCE_QSPI ?= 0 91SOCFPGA_BOOT_SOURCE_NAND ?= 0 92 93$(eval $(call assert_booleans,\ 94 $(sort \ 95 SOCFPGA_BOOT_SOURCE_SDMMC \ 96 SOCFPGA_BOOT_SOURCE_QSPI \ 97 SOCFPGA_BOOT_SOURCE_NAND \ 98))) 99$(eval $(call add_defines,\ 100 $(sort \ 101 SOCFPGA_BOOT_SOURCE_SDMMC \ 102 SOCFPGA_BOOT_SOURCE_QSPI \ 103 SOCFPGA_BOOT_SOURCE_NAND \ 104))) 105 106PROGRAMMABLE_RESET_ADDRESS := 0 107RESET_TO_BL2 := 1 108USE_COHERENT_MEM := 1 109 110#To get the TF-A version via SMC calls 111DEFINES += -DVERSION_MAJOR=${VERSION_MAJOR} 112DEFINES += -DVERSION_MINOR=${VERSION_MINOR} 113DEFINES += -DVERSION_PATCH=${VERSION_PATCH} 114