1/* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46) 32workaround_reset_end neoverse_v1, CVE(2024, 5660) 33 34check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2) 35 36workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635 37 /* Inserts a DMB SY before and after MRS PAR_EL1 */ 38 ldr x0, =0x0 39 msr NEOVERSE_V1_CPUPSELR_EL3, x0 40 ldr x0, = 0xEE070F14 41 msr NEOVERSE_V1_CPUPOR_EL3, x0 42 ldr x0, = 0xFFFF0FFF 43 msr NEOVERSE_V1_CPUPMR_EL3, x0 44 ldr x0, =0x4005027FF 45 msr NEOVERSE_V1_CPUPCR_EL3, x0 46 47 /* Inserts a DMB SY before STREX imm offset */ 48 ldr x0, =0x1 49 msr NEOVERSE_V1_CPUPSELR_EL3, x0 50 ldr x0, =0x00e8400000 51 msr NEOVERSE_V1_CPUPOR_EL3, x0 52 ldr x0, =0x00fff00000 53 msr NEOVERSE_V1_CPUPMR_EL3, x0 54 ldr x0, = 0x4001027FF 55 msr NEOVERSE_V1_CPUPCR_EL3, x0 56 57 /* Inserts a DMB SY before STREX[BHD}/STLEX* */ 58 ldr x0, =0x2 59 msr NEOVERSE_V1_CPUPSELR_EL3, x0 60 ldr x0, =0x00e8c00040 61 msr NEOVERSE_V1_CPUPOR_EL3, x0 62 ldr x0, =0x00fff00040 63 msr NEOVERSE_V1_CPUPMR_EL3, x0 64 ldr x0, = 0x4001027FF 65 msr NEOVERSE_V1_CPUPCR_EL3, x0 66 67 /* Inserts a DMB SY after STREX imm offset */ 68 ldr x0, =0x3 69 msr NEOVERSE_V1_CPUPSELR_EL3, x0 70 ldr x0, =0x00e8400000 71 msr NEOVERSE_V1_CPUPOR_EL3, x0 72 ldr x0, =0x00fff00000 73 msr NEOVERSE_V1_CPUPMR_EL3, x0 74 ldr x0, = 0x4004027FF 75 msr NEOVERSE_V1_CPUPCR_EL3, x0 76 77 /* Inserts a DMB SY after STREX[BHD}/STLEX* */ 78 ldr x0, =0x4 79 msr NEOVERSE_V1_CPUPSELR_EL3, x0 80 ldr x0, =0x00e8c00040 81 msr NEOVERSE_V1_CPUPOR_EL3, x0 82 ldr x0, =0x00fff00040 83 msr NEOVERSE_V1_CPUPMR_EL3, x0 84 ldr x0, = 0x4004027FF 85 msr NEOVERSE_V1_CPUPCR_EL3, x0 86 87workaround_reset_end neoverse_v1, ERRATUM(1618635) 88 89check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0) 90 91workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420 92 /* Set bit 53 in CPUECTLR_EL1 */ 93 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53 94workaround_reset_end neoverse_v1, ERRATUM(1774420) 95 96check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0) 97 98workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573 99 /* Set bit 2 in ACTLR2_EL1 */ 100 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2 101workaround_reset_end neoverse_v1, ERRATUM(1791573) 102 103check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0) 104 105workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267 106 /* Set bit 28 in ACTLR2_EL1 */ 107 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28 108workaround_reset_end neoverse_v1, ERRATUM(1852267) 109 110check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0) 111 112workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756 113 /* Set bit 8 in CPUECTLR_EL1 */ 114 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8 115workaround_reset_end neoverse_v1, ERRATUM(1925756) 116 117check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1) 118 119workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577 120 mov x0, #0 121 msr S3_6_C15_C8_0, x0 122 ldr x0, =0x10E3900002 123 msr S3_6_C15_C8_2, x0 124 ldr x0, =0x10FFF00083 125 msr S3_6_C15_C8_3, x0 126 ldr x0, =0x2001003FF 127 msr S3_6_C15_C8_1, x0 128 129 mov x0, #1 130 msr S3_6_C15_C8_0, x0 131 ldr x0, =0x10E3800082 132 msr S3_6_C15_C8_2, x0 133 ldr x0, =0x10FFF00083 134 msr S3_6_C15_C8_3, x0 135 ldr x0, =0x2001003FF 136 msr S3_6_C15_C8_1, x0 137 138 mov x0, #2 139 msr S3_6_C15_C8_0, x0 140 ldr x0, =0x10E3800200 141 msr S3_6_C15_C8_2, x0 142 ldr x0, =0x10FFF003E0 143 msr S3_6_C15_C8_3, x0 144 ldr x0, =0x2001003FF 145 msr S3_6_C15_C8_1, x0 146 147workaround_reset_end neoverse_v1, ERRATUM(1940577) 148 149check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1) 150 151workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096 152 mov x0, #0x3 153 msr S3_6_C15_C8_0, x0 154 ldr x0, =0xEE010F12 155 msr S3_6_C15_C8_2, x0 156 ldr x0, =0xFFFF0FFF 157 msr S3_6_C15_C8_3, x0 158 ldr x0, =0x80000000003FF 159 msr S3_6_C15_C8_1, x0 160workaround_reset_end neoverse_v1, ERRATUM(1966096) 161 162check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1) 163 164workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267 165 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 166 mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV 167 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 168 msr NEOVERSE_V1_CPUECTLR_EL1, x1 169workaround_reset_end neoverse_v1, ERRATUM(2108267) 170 171check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2) 172 173workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242 174 mov x0, #0x3 175 msr S3_6_C15_C8_0, x0 176 ldr x0, =0xEE720F14 177 msr S3_6_C15_C8_2, x0 178 ldr x0, =0xFFFF0FDF 179 msr S3_6_C15_C8_3, x0 180 ldr x0, =0x40000005003FF 181 msr S3_6_C15_C8_1, x0 182workaround_reset_end neoverse_v1, ERRATUM(2139242) 183 184check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1) 185 186workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392 187 ldr x0, =0x5 188 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 189 ldr x0, =0x10F600E000 190 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 191 ldr x0, =0x10FF80E000 192 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 193 ldr x0, =0x80000000003FF 194 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 195workaround_reset_end neoverse_v1, ERRATUM(2216392) 196 197check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1) 198 199workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912 200 /* Set bit 0 in ACTLR2_EL1 */ 201 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0 202workaround_reset_end neoverse_v1, ERRATUM(2294912) 203 204check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2) 205 206workaround_runtime_start neoverse_v1, ERRATUM(2348377), ERRATA_V1_2348377 207 /* Set bit 61 in CPUACTLR5_EL1 */ 208 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_61 209workaround_runtime_end neoverse_v1, ERRATUM(2348377) 210 211check_erratum_ls neoverse_v1, ERRATUM(2348377), CPU_REV(1, 1) 212 213workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203 214 /* Set bit 40 in ACTLR2_EL1 */ 215 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40 216workaround_reset_end neoverse_v1, ERRATUM(2372203) 217 218check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1) 219 220workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 221 /* dsb before isb of power down sequence */ 222 dsb sy 223workaround_runtime_end neoverse_v1, ERRATUM(2743093) 224 225check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2) 226 227workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233 228 sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56 229 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55 230workaround_reset_end neoverse_v1, ERRATUM(2743233) 231 232check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2) 233 234workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461 235 sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47 236workaround_reset_end neoverse_v1, ERRATUM(2779461) 237 238check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2) 239 240 241workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960 242#if IMAGE_BL31 243 /* 244 * The Neoverse-V1 generic vectors are overridden to apply errata 245 * mitigation on exception entry from lower ELs. 246 */ 247 override_vector_table wa_cve_vbar_neoverse_v1 248#endif /* IMAGE_BL31 */ 249workaround_reset_end neoverse_v1, CVE(2022,23960) 250 251check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 252 253 /* --------------------------------------------- 254 * HW will do the cache maintenance while powering down 255 * --------------------------------------------- 256 */ 257func neoverse_v1_core_pwr_dwn 258 /* --------------------------------------------- 259 * Enable CPU power down bit in power control register 260 * --------------------------------------------- 261 */ 262 sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 263 apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093, NO_GET_CPU_REV 264 265 isb 266 ret 267endfunc neoverse_v1_core_pwr_dwn 268 269cpu_reset_func_start neoverse_v1 270 /* Disable speculative loads */ 271 msr SSBS, xzr 272cpu_reset_func_end neoverse_v1 273 274 /* --------------------------------------------- 275 * This function provides Neoverse-V1 specific 276 * register information for crash reporting. 277 * It needs to return with x6 pointing to 278 * a list of register names in ascii and 279 * x8 - x15 having values of registers to be 280 * reported. 281 * --------------------------------------------- 282 */ 283.section .rodata.neoverse_v1_regs, "aS" 284neoverse_v1_regs: /* The ascii list of register names to be reported */ 285 .asciz "cpuectlr_el1", "" 286 287func neoverse_v1_cpu_reg_dump 288 adr x6, neoverse_v1_regs 289 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 290 ret 291endfunc neoverse_v1_cpu_reg_dump 292 293declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 294 neoverse_v1_reset_func, \ 295 neoverse_v1_core_pwr_dwn 296