1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. This option defaults to 256. 34FVP_TRUSTED_SRAM_SIZE := 256 35 36# Macro to enable helpers for running SPM tests. Disabled by default. 37PLAT_TEST_SPM := 0 38 39# By default dont build CPUs with no FVP model. 40BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 41 42ENABLE_FEAT_AMU := 2 43ENABLE_FEAT_AMUv1p1 := 2 44ENABLE_FEAT_HCX := 2 45ENABLE_FEAT_RNG := 2 46ENABLE_FEAT_TWED := 2 47ENABLE_FEAT_GCS := 2 48 49ifeq (${ARCH}, aarch64) 50 51ifeq (${SPM_MM}, 0) 52ifeq (${CTX_INCLUDE_FPREGS}, 0) 53 ENABLE_SME_FOR_NS := 2 54 ENABLE_SME2_FOR_NS := 2 55else 56 ENABLE_SVE_FOR_NS := 0 57 ENABLE_SME_FOR_NS := 0 58 ENABLE_SME2_FOR_NS := 0 59endif 60endif 61 62 ENABLE_BRBE_FOR_NS := 2 63 ENABLE_TRBE_FOR_NS := 2 64 ENABLE_FEAT_D128 := 2 65 ENABLE_FEAT_FPMR := 2 66 ENABLE_FEAT_MOPS := 2 67endif 68 69ENABLE_SYS_REG_TRACE_FOR_NS := 2 70ENABLE_FEAT_CSV2_2 := 2 71ENABLE_FEAT_CSV2_3 := 2 72ENABLE_FEAT_DEBUGV8P9 := 2 73ENABLE_FEAT_DIT := 2 74ENABLE_FEAT_PAN := 2 75ENABLE_FEAT_VHE := 2 76CTX_INCLUDE_NEVE_REGS := 2 77ENABLE_FEAT_SEL2 := 2 78ENABLE_TRF_FOR_NS := 2 79ENABLE_FEAT_ECV := 2 80ENABLE_FEAT_FGT := 2 81ENABLE_FEAT_FGT2 := 2 82ENABLE_FEAT_THE := 2 83ENABLE_FEAT_TCR2 := 2 84ENABLE_FEAT_S2PIE := 2 85ENABLE_FEAT_S1PIE := 2 86ENABLE_FEAT_S2POE := 2 87ENABLE_FEAT_S1POE := 2 88ENABLE_FEAT_SCTLR2 := 2 89ENABLE_FEAT_MTE2 := 2 90ENABLE_FEAT_LS64_ACCDATA := 2 91 92# The FVP platform depends on this macro to build with correct GIC driver. 93$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 94 95# Pass FVP_CLUSTER_COUNT to the build system. 96$(eval $(call add_define,FVP_CLUSTER_COUNT)) 97 98# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 99$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 100 101# Pass FVP_MAX_PE_PER_CPU to the build system. 102$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 103 104# Pass FVP_GICR_REGION_PROTECTION to the build system. 105$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 106 107# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 108$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 109 110# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 111# choose the CCI driver , else the CCN driver 112ifeq ($(FVP_CLUSTER_COUNT), 0) 113$(error "Incorrect cluster count specified for FVP port") 114else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 115FVP_INTERCONNECT_DRIVER := FVP_CCI 116else 117FVP_INTERCONNECT_DRIVER := FVP_CCN 118endif 119 120$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 121 122# Choose the GIC sources depending upon the how the FVP will be invoked 123ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 124 125# The GIC model (GIC-600 or GIC-500) will be detected at runtime 126GICV3_SUPPORT_GIC600 := 1 127GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 128 129# Include GICv3 driver files 130include drivers/arm/gic/v3/gicv3.mk 131 132FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 133 plat/common/plat_gicv3.c \ 134 plat/arm/common/arm_gicv3.c 135 136 ifeq ($(filter 1,${RESET_TO_BL2} \ 137 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 138 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 139 endif 140 141else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 142 143# No GICv4 extension 144GIC_ENABLE_V4_EXTN := 0 145$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 146 147# Include GICv2 driver files 148include drivers/arm/gic/v2/gicv2.mk 149 150FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 151 plat/common/plat_gicv2.c \ 152 plat/arm/common/arm_gicv2.c 153 154FVP_DT_PREFIX := fvp-base-gicv2-psci 155else 156$(error "Incorrect GIC driver chosen on FVP port") 157endif 158 159ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 160FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 161else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 162FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 163 plat/arm/common/arm_ccn.c 164else 165$(error "Incorrect CCN driver chosen on FVP port") 166endif 167 168FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 169 plat/arm/board/fvp/fvp_security.c \ 170 plat/arm/common/arm_tzc400.c 171 172 173PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 174 -Iinclude/lib/psa 175 176 177PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 178 179FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 180 181ifeq (${ARCH}, aarch64) 182 183# select a different set of CPU files, depending on whether we compile for 184# hardware assisted coherency cores or not 185ifeq (${HW_ASSISTED_COHERENCY}, 0) 186# Cores used without DSU 187 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 188 lib/cpus/aarch64/cortex_a53.S \ 189 lib/cpus/aarch64/cortex_a57.S \ 190 lib/cpus/aarch64/cortex_a72.S \ 191 lib/cpus/aarch64/cortex_a73.S 192else 193# Cores used with DSU only 194 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 195 # AArch64-only cores 196 # TODO: add all cores to the appropriate lists 197 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 198 lib/cpus/aarch64/cortex_a65ae.S \ 199 lib/cpus/aarch64/cortex_a76.S \ 200 lib/cpus/aarch64/cortex_a76ae.S \ 201 lib/cpus/aarch64/cortex_a77.S \ 202 lib/cpus/aarch64/cortex_a78.S \ 203 lib/cpus/aarch64/cortex_a78_ae.S \ 204 lib/cpus/aarch64/cortex_a78c.S \ 205 lib/cpus/aarch64/cortex_a710.S \ 206 lib/cpus/aarch64/cortex_a715.S \ 207 lib/cpus/aarch64/cortex_a720.S \ 208 lib/cpus/aarch64/cortex_a720_ae.S \ 209 lib/cpus/aarch64/neoverse_n_common.S \ 210 lib/cpus/aarch64/neoverse_n1.S \ 211 lib/cpus/aarch64/neoverse_n2.S \ 212 lib/cpus/aarch64/neoverse_v1.S \ 213 lib/cpus/aarch64/neoverse_e1.S \ 214 lib/cpus/aarch64/cortex_x2.S \ 215 lib/cpus/aarch64/cortex_x4.S 216 endif 217 # AArch64/AArch32 cores 218 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 219 lib/cpus/aarch64/cortex_a75.S 220endif 221 222#Build AArch64-only CPUs with no FVP model yet. 223ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 224 # travis/gelas need these 225 FEAT_PABANDON := 1 226 ERRATA_SME_POWER_DOWN := 1 227 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 228 lib/cpus/aarch64/cortex_gelas.S \ 229 lib/cpus/aarch64/nevis.S \ 230 lib/cpus/aarch64/travis.S \ 231 lib/cpus/aarch64/cortex_arcadia.S \ 232 lib/cpus/aarch64/cortex_alto.S 233endif 234 235else 236FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 237 lib/cpus/aarch32/cortex_a57.S \ 238 lib/cpus/aarch32/cortex_a53.S 239endif 240 241BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 242 drivers/arm/sp805/sp805.c \ 243 drivers/delay_timer/delay_timer.c \ 244 drivers/io/io_semihosting.c \ 245 lib/semihosting/semihosting.c \ 246 lib/semihosting/${ARCH}/semihosting_call.S \ 247 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 248 plat/arm/board/fvp/fvp_bl1_setup.c \ 249 plat/arm/board/fvp/fvp_cpu_pwr.c \ 250 plat/arm/board/fvp/fvp_err.c \ 251 plat/arm/board/fvp/fvp_io_storage.c \ 252 plat/arm/board/fvp/fvp_topology.c \ 253 ${FVP_CPU_LIBS} \ 254 ${FVP_INTERCONNECT_SOURCES} 255 256ifeq (${USE_SP804_TIMER},1) 257BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 258else 259BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 260endif 261 262 263BL2_SOURCES += drivers/arm/sp805/sp805.c \ 264 drivers/io/io_semihosting.c \ 265 lib/utils/mem_region.c \ 266 lib/semihosting/semihosting.c \ 267 lib/semihosting/${ARCH}/semihosting_call.S \ 268 plat/arm/board/fvp/fvp_bl2_setup.c \ 269 plat/arm/board/fvp/fvp_err.c \ 270 plat/arm/board/fvp/fvp_io_storage.c \ 271 plat/arm/common/arm_nor_psci_mem_protect.c \ 272 ${FVP_SECURITY_SOURCES} 273 274 275ifeq (${COT_DESC_IN_DTB},1) 276BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 277endif 278 279ifeq (${ENABLE_RME},1) 280BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 281 plat/arm/board/fvp/fvp_cpu_pwr.c 282 283BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 284 plat/arm/board/fvp/fvp_realm_attest_key.c \ 285 plat/arm/board/fvp/fvp_el3_token_sign.c 286endif 287 288ifeq (${ENABLE_FEAT_RNG_TRAP},1) 289BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 290endif 291 292ifeq (${RESET_TO_BL2},1) 293BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 294 plat/arm/board/fvp/fvp_cpu_pwr.c \ 295 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 296 ${FVP_CPU_LIBS} \ 297 ${FVP_INTERCONNECT_SOURCES} 298endif 299 300ifeq (${USE_SP804_TIMER},1) 301BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 302endif 303 304BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 305 ${FVP_SECURITY_SOURCES} 306 307ifeq (${USE_SP804_TIMER},1) 308BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 309endif 310 311BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 312 drivers/arm/smmu/smmu_v3.c \ 313 drivers/delay_timer/delay_timer.c \ 314 drivers/cfi/v2m/v2m_flash.c \ 315 lib/utils/mem_region.c \ 316 plat/arm/board/fvp/fvp_bl31_setup.c \ 317 plat/arm/board/fvp/fvp_console.c \ 318 plat/arm/board/fvp/fvp_pm.c \ 319 plat/arm/board/fvp/fvp_topology.c \ 320 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 321 plat/arm/board/fvp/fvp_cpu_pwr.c \ 322 plat/arm/common/arm_nor_psci_mem_protect.c \ 323 ${FVP_CPU_LIBS} \ 324 ${FVP_GIC_SOURCES} \ 325 ${FVP_INTERCONNECT_SOURCES} \ 326 ${FVP_SECURITY_SOURCES} 327 328# Support for fconf in BL31 329# Added separately from the above list for better readability 330ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 331BL31_SOURCES += lib/fconf/fconf.c \ 332 lib/fconf/fconf_dyn_cfg_getter.c \ 333 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 334 335BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 336 337ifeq (${SEC_INT_DESC_IN_FCONF},1) 338BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 339endif 340 341endif 342 343ifeq (${USE_SP804_TIMER},1) 344BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 345else 346BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 347endif 348 349# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 350FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 351 352FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 353$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 354 355ifeq (${TRANSFER_LIST}, 0) 356FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 357 ${PLAT}_fw_config.dts \ 358 ${PLAT}_tb_fw_config.dts \ 359 ${PLAT}_soc_fw_config.dts \ 360 ${PLAT}_nt_fw_config.dts \ 361 ) 362 363FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 364FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 365FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 366FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 367 368ifeq (${SPD},tspd) 369FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 370FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 371 372# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 374endif 375 376ifeq (${SPD},spmd) 377 378ifeq ($(ARM_SPMC_MANIFEST_DTS),) 379ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 380endif 381 382FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 383FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 384 385# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 387endif 388 389# Add the FW_CONFIG to FIP and specify the same to certtool 390$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 391# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 392$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 393# Add the NT_FW_CONFIG to FIP and specify the same to certtool 394$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 395# Add the TB_FW_CONFIG to FIP and specify the same to certtool 396$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 397endif 398 399# Add the HW_CONFIG to FIP and specify the same to certtool 400$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 401 402ifeq (${TRANSFER_LIST}, 1) 403include lib/transfer_list/transfer_list.mk 404 405ifeq ($(RESET_TO_BL31), 1) 406HW_CONFIG := ${FVP_HW_CONFIG} 407FW_HANDOFF_SIZE := 20000 408 409TRANSFER_LIST_DTB_OFFSET := 0x20 410$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 411endif 412endif 413 414ifeq (${HOB_LIST}, 1) 415include lib/hob/hob.mk 416endif 417 418# Enable dynamic mitigation support by default 419DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 420 421ifneq (${ENABLE_FEAT_AMU},0) 422BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 423 lib/cpus/aarch64/cpuamu_helpers.S 424 425ifeq (${HW_ASSISTED_COHERENCY}, 1) 426BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 427 lib/cpus/aarch64/neoverse_n1_pubsub.c 428endif 429endif 430 431ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 432 ifeq (${ENABLE_FEAT_RAS},1) 433 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 434 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 435 else 436 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 437 endif 438 else 439 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 440 endif 441endif 442 443ifneq (${ENABLE_STACK_PROTECTOR},0) 444PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 445endif 446 447# Enable the dynamic translation tables library. 448ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 449 ifeq (${ARCH},aarch32) 450 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 451 else # AArch64 452 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 453 endif 454endif 455 456ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 457 ifeq (${ARCH},aarch32) 458 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 459 else # AArch64 460 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 461 ifeq (${SPD},tspd) 462 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 463 endif 464 endif 465endif 466 467ifeq (${USE_DEBUGFS},1) 468 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 469endif 470 471# Add support for platform supplied linker script for BL31 build 472$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 473 474ifneq (${RESET_TO_BL2}, 0) 475 override BL1_SOURCES = 476endif 477 478include plat/arm/board/common/board_common.mk 479include plat/arm/common/arm_common.mk 480 481ifeq (${MEASURED_BOOT},1) 482BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 483 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 484 lib/psa/measured_boot.c 485 486BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 487 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 488 lib/psa/measured_boot.c 489endif 490 491ifeq (${DRTM_SUPPORT}, 1) 492BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 493 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 494 plat/arm/board/fvp/fvp_drtm_err.c \ 495 plat/arm/board/fvp/fvp_drtm_measurement.c \ 496 plat/arm/board/fvp/fvp_drtm_stub.c \ 497 plat/arm/common/arm_dyn_cfg.c \ 498 plat/arm/board/fvp/fvp_err.c 499endif 500 501ifeq (${TRUSTED_BOARD_BOOT}, 1) 502BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 503BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 504 505# FVP being a development platform, enable capability to disable Authentication 506# dynamically if TRUSTED_BOARD_BOOT is set. 507DYN_DISABLE_AUTH := 1 508endif 509 510ifeq (${SPMC_AT_EL3}, 1) 511PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 512endif 513 514PSCI_OS_INIT_MODE := 1 515 516ifeq (${SPD},spmd) 517BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 518endif 519 520# Test specific macros, keep them at bottom of this file 521$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 522ifeq (${PLATFORM_TEST_EA_FFH}, 1) 523 ifeq (${FFH_SUPPORT}, 0) 524 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 525 endif 526 527endif 528 529$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 530ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 531 ifeq (${ENABLE_FEAT_RAS}, 0) 532 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 533 endif 534 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 535 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 536 endif 537endif 538 539$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 540ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 541 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 542 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 543 endif 544 ifeq (${ENABLE_SPMD_LP}, 0) 545 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 546 endif 547 ifeq (${ENABLE_FEAT_RAS}, 0) 548 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 549 endif 550 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 551 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 552 endif 553endif 554 555ifeq (${ERRATA_ABI_SUPPORT}, 1) 556include plat/arm/board/fvp/fvp_cpu_errata.mk 557endif 558 559# Build macro necessary for running SPM tests on FVP platform 560$(eval $(call add_define,PLAT_TEST_SPM)) 561