1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53For example: `Cortex-A72 MPCore Software Developers Errata Notice`_ 54 55The errata workarounds are implemented for a particular revision or a set of 56processor revisions. This is checked by the reset handler at runtime. Each 57errata workaround is identified by its ``ID`` as specified in the processor's 58errata notice document. The format of the define used to enable/disable the 59errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 60is for example ``A57`` for the ``Cortex_A57`` CPU. 61 62Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 63write errata workaround functions. 64 65All workarounds are disabled by default. The platform is responsible for 66enabling these workarounds according to its requirement by defining the 67errata workaround build flags in the platform specific makefile. In case 68these workarounds are enabled for the wrong CPU revision then the errata 69workaround is not applied. In the DEBUG build, this is indicated by 70printing a warning to the crash console. 71 72In the current implementation, a platform which has more than 1 variant 73with different revisions of a processor has no runtime mechanism available 74for it to specify which errata workarounds should be enabled or not. 75 76The value of the build flags is 0 by default, that is, disabled. A value of 1 77will enable it. 78 79For Cortex-A9, the following errata build flags are defined : 80 81- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 82 CPU. This needs to be enabled for all revisions of the CPU. 83 84For Cortex-A15, the following errata build flags are defined : 85 86- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 87 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 88 89- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92For Cortex-A17, the following errata build flags are defined : 93 94- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 95 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 96 97- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100For Cortex-A35, the following errata build flags are defined : 101 102- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 103 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 104 105For Cortex-A53, the following errata build flags are defined : 106 107- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 108 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 109 110- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 114 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 115 116- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 117 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 118 119- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 120 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 121 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 122 sections. 123 124- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 125 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 126 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 127 ``A53_DISABLE_NON_TEMPORAL_HINT``. 128 129- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 130 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 131 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 132 which are 4kB aligned. 133 134- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 135 CPUs. Though the erratum is present in every revision of the CPU, 136 this workaround is only applied to CPUs from r0p3 onwards, which feature 137 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 138 Earlier revisions of the CPU have other errata which require the same 139 workaround in software, so they should be covered anyway. 140 141- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 142 revisions of Cortex-A53 CPU. 143 144For Cortex-A55, the following errata build flags are defined : 145 146- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 157 158- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 163 164- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 165 revisions of Cortex-A55 CPU. 166 167For Cortex-A57, the following errata build flags are defined : 168 169- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 183 184- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 195 196- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 201 202- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 203 revisions of Cortex-A57 CPU. 204 205For Cortex-A72, the following errata build flags are defined : 206 207- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 208 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 209 210- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 211 revisions of Cortex-A72 CPU. 212 213For Cortex-A73, the following errata build flags are defined : 214 215- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 216 CPU. This needs to be enabled only for revision r0p0 of the CPU. 217 218- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 219 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 220 221For Cortex-A75, the following errata build flags are defined : 222 223- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 224 CPU. This needs to be enabled only for revision r0p0 of the CPU. 225 226- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 227 CPU. This needs to be enabled only for revision r0p0 of the CPU. 228 229For Cortex-A76, the following errata build flags are defined : 230 231- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 232 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 233 234- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 235 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 236 237- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 238 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 239 240- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 241 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 242 243- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 244 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 245 246- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 247 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 248 249- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 250 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 251 252- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 253 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 254 255- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 256 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 257 limitation of errata framework this errata is applied to all revisions 258 of Cortex-A76 CPU. 259 260- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 261 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 262 263- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 264 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 265 266- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 267 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 268 still open. 269 270For Cortex-A77, the following errata build flags are defined : 271 272- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 273 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 274 275- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 276 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 277 278- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 279 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 280 281- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 282 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 283 284- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 285 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 286 287 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 288 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 289 290 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 291 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 292 293For Cortex-A78, the following errata build flags are defined : 294 295- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 296 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 297 298- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 299 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 300 301- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 302 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 303 issue but there is no workaround for that revision. 304 305- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 306 CPU. This needs to be enabled for revisions r0p0 and r1p0. 307 308- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 309 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 310 311- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 312 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 313 is present in r0p0 but there is no workaround. It is still open. 314 315- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 316 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 317 it is still open. 318 319- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 320 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 321 it is still open. 322 323- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 324 CPU, this erratum affects system configurations that do not use an ARM 325 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 326 and r1p2 and it is still open. 327 328- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 329 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 330 it is still open. 331 332- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 333 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 334 it is still open. 335 336- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 337 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 338 it is still open. 339 340For Cortex-A78AE, the following errata build flags are defined : 341 342- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 343 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 344 This erratum is still open. 345 346- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 347 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 348 erratum is still open. 349 350- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 351 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 352 This erratum is still open. 353 354- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 355 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 356 erratum is still open. 357 358- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 359 Cortex-A78AE CPU. This erratum affects system configurations that do not use 360 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 361 r0p2. This erratum is still open. 362 363For Cortex-A78C, the following errata build flags are defined : 364 365- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 366 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 367 fixed in r0p1. 368 369- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 370 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 371 fixed in r0p1. 372 373- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 374 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 375 it is still open. 376 377- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 378 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 379 erratum is still open. 380 381- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 382 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 383 erratum is still open. 384 385- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 386 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 387 erratum is still open. 388 389- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 390 Cortex-A78C CPU, this erratum affects system configurations that do not use 391 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 392 and is still open. 393 394- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 395 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 396 This erratum is still open. 397 398- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 399 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 400 This erratum is still open. 401 402- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 403 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 404 This erratum is still open. 405 406For Cortex-X1 CPU, the following errata build flags are defined: 407 408- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 409 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 410 411- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 412 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 413 414- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 415 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 416 417For Neoverse N1, the following errata build flags are defined : 418 419- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 420 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 421 422- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 423 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 424 425- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 426 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 427 428- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 429 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 430 431- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 432 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 433 434- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 435 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 436 437- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 438 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 439 440- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 441 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 442 443- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 444 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 445 446- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 447 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 448 449- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 450 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 451 452- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 453 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 454 455- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 456 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 457 revisions r0p0, r1p0, and r2p0 there is no workaround. 458 459- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 460 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 461 still open. 462 463For Neoverse V1, the following errata build flags are defined : 464 465- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 466 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 467 r1p0. 468 469- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 470 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 471 in r1p1. 472 473- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 474 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 475 in r1p1. 476 477- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 478 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 479 in r1p1. 480 481- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 482 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 483 484- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 485 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 486 CPU. 487 488- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 489 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 490 issue is present in r0p0 as well but there is no workaround for that 491 revision. It is still open. 492 493- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 494 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 495 CPU. It is still open. 496 497- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 498 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 499 issue is present in r0p0 as well but there is no workaround for that 500 revision. It is still open. 501 502- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 503 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 504 the CPU. 505 506- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 507 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 508 It has been fixed in r1p2. 509 510- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 511 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 512 It is still open. 513 514- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 515 CPU, this erratum affects system configurations that do not use an ARM 516 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 517 It has been fixed in r1p2. 518 519- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 520 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 521 CPU. It is still open. 522 523- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 524 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 525 CPU. It is still open. 526 527- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 528 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 529 CPU. It is still open. 530 531For Neoverse V2, the following errata build flags are defined : 532 533- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 534 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 535 r0p2. 536 537- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 538 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 539 r0p2. 540 541- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 542 CPU, this affects system configurations that do not use and ARM interconnect 543 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 544 in r0p2. 545 546- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 547 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 548 r0p2. 549 550- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 551 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 552 r0p2. 553 554- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 555 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 556 r0p2. 557 558- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 559 CPU, this affects all configurations. This needs to be enabled for revisions 560 r0p0 and r0p1. It has been fixed in r0p2. 561 562- ``ERRATA_V2_3701771``: This applies errata 3701771 workaround to Neoverse-V2 563 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is 564 still open. 565 566- ``ERRATA_V2_3841324``: This applies errata 3841324 workaround to Neoverse-V2 567 CPU. This needs to be enabled only for revisions r0p0 and r0p1 of 568 the CPU. It is fixed in r0p2. 569 570For Neoverse V3, the following errata build flags are defined : 571 572- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 573 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 574 575- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 576 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 577 is still open. 578 579For Cortex-A710, the following errata build flags are defined : 580 581- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to 582 Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has 583 been fixed in r2p0. 584 585- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to 586 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 587 It has been fixed in r2p0. 588 589- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to 590 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 591 It has been fixed in r2p0. 592 593- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to 594 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 595 It has been fixed in r2p0. 596 597- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 598 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 599 r2p0 of the CPU. It is still open. 600 601- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 602 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 603 r2p0 of the CPU. It is still open. 604 605- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 606 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 607 and is still open. 608 609- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 610 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 611 of the CPU and is still open. 612 613- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 614 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 615 is still open. 616 617- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 618 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 619 of the CPU and is fixed in r2p1. 620 621- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 622 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 623 of the CPU and is fixed in r2p1. 624 625- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 626 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 627 and is fixed in r2p1. 628 629- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 630 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 631 of the CPU and is fixed in r2p1. 632 633- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 634 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 635 r2p1 of the CPU and is still open. 636 637- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 638 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 639 of the CPU and is fixed in r2p1. 640 641- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 642 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 643 of the CPU and is fixed in r2p1. 644 645- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 646 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 647 of the CPU and is fixed in r2p1. 648 649- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 650 CPU, and applies to system configurations that do not use and ARM 651 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 652 is still open. 653 654- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 655 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 656 r2p1 of the CPU and is still open. 657 658- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 659 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 660 r2p1 of the CPU and is still open. 661 662- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 663 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 664 CPU and is still open. 665 666- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 667 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 668 CPU and is still open. 669 670For Neoverse N2, the following errata build flags are defined : 671 672- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 673 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 674 675- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 676 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 677 678- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 679 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 680 681- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 682 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 683 684- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 685 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 686 687- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 688 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 689 690- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 691 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 692 693- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 694 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 695 696- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 697 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 698 699- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 700 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 701 702- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 703 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 704 r0p1. 705 706- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 707 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 708 r0p1. 709 710- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 711 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 712 it is fixed in r0p3. 713 714- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 715 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 716 717- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 718 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 719 r0p1. 720 721- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 722 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 723 in r0p3. 724 725- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 726 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 727 in r0p3. 728 729- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 730 CPU, this erratum affects system configurations that do not use and ARM 731 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 732 It is fixed in r0p3. 733 734- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 735 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 736 in r0p3. 737 738- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 739 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 740 still open. 741 742For Neoverse N3, the following errata build flags are defined : 743 744- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 745 CPU. This needs to be enabled for revisions r0p0 and is still open. 746 747For Cortex-X2, the following errata build flags are defined : 748 749- ``ERRATA_X2_1901946``: This applies errata 1901946 workaround to Cortex-X2 750 CPU. This needs to be enabled only for r1p0, it is fixed in r2p0. 751 752- ``ERRATA_X2_1916945``: This applies errata 1916945 workaround to Cortex-X2 753 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 754 is fixed in r2p0. 755 756- ``ERRATA_X2_1917258``: This applies errata 1917258 workaround to Cortex-X2 757 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 758 is fixed in r2p0. 759 760- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2 761 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 762 is fixed in r2p0. 763 764- ``ERRATA_X2_1934260``: This applies errata 1934260 workaround to Cortex-X2 765 CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed 766 in r2p0. 767 768- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 769 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 770 CPU, it is fixed in r2p1. 771 772- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 773 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 774 CPU, it is fixed in r2p1. 775 776- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 777 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 778 CPU, it is fixed in r2p1. 779 780- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 781 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 782 in r2p1. 783 784- ``ERRATA_X2_2136059``: This applies errata 2136059 workaround to Cortex-X2 785 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 786 CPU, it is fixed in r2p1. 787 788- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 789 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 790 in r2p1. 791 792- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 793 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 794 CPU, it is fixed in r2p1. 795 796- ``ERRATA_X2_2267065``: This applies errata 2267065 workaround to Cortex-X2 797 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 798 CPU, it is fixed in r2p1. 799 800- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 801 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 802 CPU and is still open. 803 804- ``ERRATA_X2_2291219``: This applies errata 2291219 workaround to Cortex-X2 805 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 806 CPU, it is fixed in r2p1. 807 808- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 809 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 810 CPU, it is fixed in r2p1. 811 812- ``ERRATA_X2_2701952``: This applies errata 2701952 workaround to Cortex-X2 813 CPU and affects system configurations that do not use an Arm interconnect IP. 814 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 815 still open. 816 817- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 818 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 819 CPU and is still open. 820 821- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 822 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 823 CPU and is still open. 824 825- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 826 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 827 CPU and is still open. 828 829- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 830 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 831 CPU and is still open. 832 833For Cortex-X3, the following errata build flags are defined : 834 835- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 836 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 837 is fixed in r1p1. 838 839- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 840 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 841 fixed in r1p2. 842 843- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 844 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 845 of the CPU, it is fixed in r1p1. 846 847- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 848 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 849 of the CPU, it is fixed in r1p1. 850 851- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 852 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 853 CPU, it is fixed in r1p2. 854 855- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 856 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 857 It is fixed in r1p1. 858 859- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 860 CPU and affects system configurations that do not use an ARM interconnect 861 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 862 in r1p2. 863 864- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 865 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 866 r1p1. It is fixed in r1p2. 867 868- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 869 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 870 fixed in r1p2. 871 872- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 873 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 874 CPU. It is fixed in r1p2. 875 876- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3 877 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 878 of the CPU. It is still open. 879 880- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3 881 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 882 of the CPU. It is still open. 883 884- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 885 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 886 of the CPU and it is still open. 887 888- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3 889 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of 890 the CPU. It is fixed in r1p2. 891 892For Cortex-X4, the following errata build flags are defined : 893 894- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 895 CPU and affects system configurations that do not use an Arm interconnect IP. 896 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 897 The workaround for this erratum is not implemented in EL3, but the flag can 898 be enabled/disabled at the platform level. The flag is used when the errata ABI 899 feature is enabled and can assist the Kernel in the process of 900 mitigation of the erratum. 901 902- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 903 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 904 r0p2. 905 906- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 907 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 908 in r0p2. 909 910- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 911 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 912 913- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 914 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 915 916- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 917 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 918 919- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 920 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 921 922- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 923 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 924 925- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 926 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 927 928- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4 929 CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3. 930 931- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 932 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 933 It is still open. 934 935- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4 936 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3. 937 It is still open. 938 939For Cortex-X925, the following errata build flags are defined : 940 941- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 942 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 943 944- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 945 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 946 947For Cortex-A510, the following errata build flags are defined : 948 949- ``ERRATA_A510_2008766``: This applies errata 2008766 workaround to 950 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 951 r0p3, r1p0, r1p1, r1p2 and r1p3. It is still open. 952 953- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 954 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 955 r0p2, r0p3 and r1p0, it is fixed in r1p1. 956 957- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 958 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 959 r0p2, it is fixed in r0p3. 960 961- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 962 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 963 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 964 workaround for those revisions. 965 966- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 967 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 968 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 969 workaround for those revisions. 970 971- ``ERRATA_A510_2169012``: This applies errata 2169012 workaround to 972 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 973 r0p2, r0p3 and r1p0, it is fixed in r1p1. 974 975- ``ERRATA_A510_2218134``: This applies errata 2218134 workaround to 976 Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed 977 in r1p1. 978 979- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 980 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 981 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 982 ENABLE_MPMM=1. 983 984- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 985 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 986 r0p3 and r1p0, it is fixed in r1p1. 987 988- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 989 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 990 r0p3 and r1p0, it is fixed in r1p1. 991 992- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 993 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 994 r0p3, r1p0 and r1p1. It is fixed in r1p2. 995 996- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 997 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 998 r0p3, r1p0, r1p1, and is fixed in r1p2. 999 1000- ``ERRATA_A510_2420992``: This applies errata 2420992 workaround to 1001 Cortex-A510 CPU. This needs to applied for revisions r1p0 and r1p1, and is 1002 fixed in r1p2. 1003 1004- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 1005 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1006 r0p3, r1p0, r1p1. It is fixed in r1p2. 1007 1008- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 1009 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 1010 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 1011 1012- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 1013 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1014 r1p0, r1p1, r1p2 and r1p3 and is still open. 1015 1016- ``ERRATA_A510_3672349``: This applies erratum 3672349 workaround to 1017 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1018 r1p0, r1p1, r1p2 and r1p3 and is still open. 1019 1020- ``ERRATA_A510_3704847``: This applies erratum 3704847 workaround to 1021 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1022 r1p0, r1p1, r1p2 and r1p3 and is still open. 1023 1024For Cortex-A520, the following errata build flags are defined : 1025 1026- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 1027 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 1028 CPU and is still open. 1029 1030- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 1031 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1032 It is still open. 1033 1034- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 1035 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1036 It is fixed in r0p2. 1037 1038For Cortex-A715, the following errata build flags are defined : 1039 1040- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 1041 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 1042 It is fixed in r1p1. 1043 1044- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 1045 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1046 fixed in r1p1. 1047 1048- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 1049 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 1050 when SPE(Statistical profiling extension)=True. The errata is fixed 1051 in r1p1. 1052 1053- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 1054 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1055 It is fixed in r1p1. 1056 1057- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 1058 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 1059 workaround for revision r0p0. It is fixed in r1p1. 1060 1061- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1062 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1063 It is fixed in r1p1. 1064 1065- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1066 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1067 and r1p1. It is fixed in r1p2. 1068 1069- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1070 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1071 r1p1 and r1p2. It is fixed in r1p3. 1072 1073- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1074 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1075 r1p2 and r1p3. It is still open. 1076 1077For Cortex-A720, the following errata build flags are defined : 1078 1079- ``ERRATA_A720_2729604``: This applies errata 2729604 workaround to 1080 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1081 It is fixed in r0p2. 1082 1083- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1084 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1085 It is fixed in r0p2. 1086 1087- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1088 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1089 It is fixed in r0p2. 1090 1091- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1092 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1093 It is fixed in r0p2. 1094 1095- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1096 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1097 It is fixed in r0p2. 1098 1099- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1100 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1101 and r0p2. It is still open. 1102 1103- ``ERRATA_A720_3711910``: This applies errata 3711910 workaround to 1104 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1105 and r0p2. It is still open. 1106 1107For Cortex-A720_AE, the following errata build flags are defined : 1108 1109- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1110 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1111 It is still open. 1112 1113For Cortex-A725, the following errata build flags are defined : 1114 1115- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1116 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1117 It is fixed in r0p2. 1118 1119DSU Errata Workarounds 1120---------------------- 1121 1122Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1123Shared Unit) errata. The DSU errata details can be found in the respective Arm 1124documentation: 1125 1126- `Arm DSU Software Developers Errata Notice`_. 1127 1128Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1129document. Thus, the build flags which enable/disable the errata workarounds 1130have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1131of DSU errata workarounds are similar to `CPU errata workarounds`_. 1132 1133For DSU errata, the following build flags are defined: 1134 1135- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1136 affected DSU configurations. This errata applies only for those DSUs that 1137 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1138 workaround results in increased DSU power consumption on idle. 1139 1140- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1141 affected DSU configurations. This errata applies only for those DSUs that 1142 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1143 r2p0 it is fixed). However, please note that this workaround results in 1144 increased DSU power consumption on idle. 1145 1146- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1147 affected DSU configurations. This errata applies for those DSUs with 1148 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1149 please note that this workaround results in increased DSU power consumption 1150 on idle. 1151 1152- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the 1153 affected DSU-120 configurations. This erratum applies to some r2p0 1154 implementations and is fixed in r2p1. The affected r2p0 implementations 1155 are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit 1156 and making sure it's clear. 1157 1158CPU Specific optimizations 1159-------------------------- 1160 1161This section describes some of the optimizations allowed by the CPU micro 1162architecture that can be enabled by the platform as desired. 1163 1164- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1165 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1166 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1167 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1168 is a known safe deviation from the Cortex-A57 TRM defined power down 1169 sequence. Each Cortex-A57 based platform must make its own decision on 1170 whether to use the optimization. 1171 1172- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1173 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1174 in a way most programmers expect, and will most probably result in a 1175 significant speed degradation to any code that employs them. The Armv8-A 1176 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1177 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1178 flag enforces this behaviour. This needs to be enabled only for revisions 1179 <= r0p3 of the CPU and is enabled by default. 1180 1181- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1182 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1183 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1184 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1185 `Cortex-A57 Software Optimization Guide`_. 1186 1187- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1188 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1189 this bit only if their memory system meets the requirement that cache 1190 line fill requests from the Cortex-A57 processor are atomic. Each 1191 Cortex-A57 based platform must make its own decision on whether to use 1192 the optimization. This flag is disabled by default. 1193 1194- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1195 level cache(LLC) is present in the system, and that the DataSource field 1196 on the master CHI interface indicates when data is returned from the LLC. 1197 This is used to control how the LL_CACHE* PMU events count. 1198 Default value is 0 (Disabled). 1199 1200- ``NEOVERSE_N2_PREFETCHER_DISABLE``: This flag disables the region prefetcher 1201 on the Neoverse N2 core. This is used during performance analysis to get clean 1202 and repeatable measurements of the cache by preventing speculative data fetches 1203 from interfering with benchmark results. 1204 Default value is 0 (Disabled). 1205 1206GIC Errata Workarounds 1207---------------------- 1208- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1209 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1210 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1211 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1212 then this flag is enabled; otherwise, it is 0 (Disabled). 1213 1214-------------- 1215 1216*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* 1217 1218.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1219.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1220.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1221.. _Cortex-A72 MPCore Software Developers Errata Notice: https://developer.arm.com/documentation/epm012079/latest 1222.. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015 1223.. _Arm DSU Software Developers Errata Notice: https://developer.arm.com/documentation/SDEN854652 1224