1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_a710_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_a710 33 34workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946 35 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_a710, ERRATUM(1901946) 37 38check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945 41 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8) 42workaround_reset_end cortex_a710, ERRATUM(1916945) 43 44check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0) 45 46workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258 47 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(43) 48workaround_reset_end cortex_a710, ERRATUM(1917258) 49 50check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0) 51 52workaround_reset_start cortex_a710, ERRATUM(1927200), ERRATA_A710_1927200 53 mov x0, #0 54 msr S3_6_C15_C8_0, x0 55 ldr x0, =0x10E3900002 56 msr S3_6_C15_C8_2, x0 57 ldr x0, =0x10FFF00083 58 msr S3_6_C15_C8_3, x0 59 ldr x0, =0x2001003FF 60 msr S3_6_C15_C8_1, x0 61 62 mov x0, #1 63 msr S3_6_C15_C8_0, x0 64 ldr x0, =0x10E3800082 65 msr S3_6_C15_C8_2, x0 66 ldr x0, =0x10FFF00083 67 msr S3_6_C15_C8_3, x0 68 ldr x0, =0x2001003FF 69 msr S3_6_C15_C8_1, x0 70 71 mov x0, #2 72 msr S3_6_C15_C8_0, x0 73 ldr x0, =0x10E3800200 74 msr S3_6_C15_C8_2, x0 75 ldr x0, =0x10FFF003E0 76 msr S3_6_C15_C8_3, x0 77 ldr x0, =0x2001003FF 78 msr S3_6_C15_C8_1, x0 79workaround_reset_end cortex_a710, ERRATUM(1927200) 80 81check_erratum_ls cortex_a710, ERRATUM(1927200), CPU_REV(1, 0) 82 83workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 84 ldr x0,=0x6 85 msr S3_6_c15_c8_0,x0 86 ldr x0,=0xF3A08002 87 msr S3_6_c15_c8_2,x0 88 ldr x0,=0xFFF0F7FE 89 msr S3_6_c15_c8_3,x0 90 ldr x0,=0x40000001003ff 91 msr S3_6_c15_c8_1,x0 92 ldr x0,=0x7 93 msr S3_6_c15_c8_0,x0 94 ldr x0,=0xBF200000 95 msr S3_6_c15_c8_2,x0 96 ldr x0,=0xFFEF0000 97 msr S3_6_c15_c8_3,x0 98 ldr x0,=0x40000001003f3 99 msr S3_6_c15_c8_1,x0 100workaround_reset_end cortex_a710, ERRATUM(1987031) 101 102check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 103 104workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 105 /* Stash ERRSELR_EL1 in x2 */ 106 mrs x2, ERRSELR_EL1 107 108 /* Select error record 0 and clear ED bit */ 109 msr ERRSELR_EL1, xzr 110 mrs x1, ERXCTLR_EL1 111 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 112 msr ERXCTLR_EL1, x1 113 114 /* Select error record 1 and clear ED bit */ 115 mov x0, #1 116 msr ERRSELR_EL1, x0 117 mrs x1, ERXCTLR_EL1 118 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 119 msr ERXCTLR_EL1, x1 120 121 /* Restore ERRSELR_EL1 from x2 */ 122 msr ERRSELR_EL1, x2 123workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 124 125check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 126 127workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 128 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 129workaround_reset_end cortex_a710, ERRATUM(2017096) 130 131check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 132 133workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 134 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 135workaround_reset_end cortex_a710, ERRATUM(2055002) 136 137check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 138 139workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 140 ldr x0,=0x3 141 msr S3_6_c15_c8_0,x0 142 ldr x0,=0xF3A08002 143 msr S3_6_c15_c8_2,x0 144 ldr x0,=0xFFF0F7FE 145 msr S3_6_c15_c8_3,x0 146 ldr x0,=0x10002001003FF 147 msr S3_6_c15_c8_1,x0 148 ldr x0,=0x4 149 msr S3_6_c15_c8_0,x0 150 ldr x0,=0xBF200000 151 msr S3_6_c15_c8_2,x0 152 ldr x0,=0xFFEF0000 153 msr S3_6_c15_c8_3,x0 154 ldr x0,=0x10002001003F3 155 msr S3_6_c15_c8_1,x0 156workaround_reset_end cortex_a710, ERRATUM(2081180) 157 158check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 159 160workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 161 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 162workaround_reset_end cortex_a710, ERRATUM(2083908) 163 164check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 165 166workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 167 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 168workaround_reset_end cortex_a710, ERRATUM(2136059) 169 170check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 171 172workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 173 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 174workaround_reset_end cortex_a710, ERRATUM(2147715) 175 176check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 177 178workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 179 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 180 181 ldr x0,=0x5 182 msr CORTEX_A710_CPUPSELR_EL3, x0 183 ldr x0,=0x10F600E000 184 msr CORTEX_A710_CPUPOR_EL3, x0 185 ldr x0,=0x10FF80E000 186 msr CORTEX_A710_CPUPMR_EL3, x0 187 ldr x0,=0x80000000003FF 188 msr CORTEX_A710_CPUPCR_EL3, x0 189workaround_reset_end cortex_a710, ERRATUM(2216384) 190 191check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 192 193workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 194 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 195workaround_reset_end cortex_a710, ERRATUM(2267065) 196 197check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 198 199workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 200 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 201workaround_reset_end cortex_a710, ERRATUM(2282622) 202 203check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 204 205.global erratum_cortex_a710_2291219_wa 206workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 207 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 208 * the workaround. Second call clears it to undo it. */ 209 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 210workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 211 212check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 213 214workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 215 errata_dsu_2313941_wa_impl 216workaround_reset_end cortex_a710, ERRATUM(2313941) 217 218check_erratum_custom_start cortex_a710, ERRATUM(2313941) 219 check_errata_dsu_2313941_impl 220 ret 221check_erratum_custom_end cortex_a710, ERRATUM(2313941) 222 223workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 224 /* Set bit 40 in CPUACTLR2_EL1 */ 225 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 226workaround_reset_end cortex_a710, ERRATUM(2371105) 227 228check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 229 230workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 231 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 232 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 233 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 234workaround_reset_end cortex_a710, ERRATUM(2742423) 235 236check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 237 238workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 239 /* dsb before isb of power down sequence */ 240 dsb sy 241workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 242 243check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 244 245workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 246 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 247workaround_reset_end cortex_a710, ERRATUM(2778471) 248 249check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 250 251add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 252 253check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 254 255workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 256#if IMAGE_BL31 257 /* 258 * The Cortex-A710 generic vectors are overridden to apply errata 259 * mitigation on exception entry from lower ELs. 260 */ 261 override_vector_table wa_cve_vbar_cortex_a710 262#endif /* IMAGE_BL31 */ 263workaround_reset_end cortex_a710, CVE(2022, 23960) 264 265check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 266 267/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 268workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 269 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 270workaround_reset_end cortex_a710, CVE(2024, 5660) 271 272check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 273 274 /* ---------------------------------------------------- 275 * HW will do the cache maintenance while powering down 276 * ---------------------------------------------------- 277 */ 278func cortex_a710_core_pwr_dwn 279 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 280 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 281 282 /* --------------------------------------------------- 283 * Enable CPU power down bit in power control register 284 * --------------------------------------------------- 285 */ 286 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 287 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 288 isb 289 ret 290endfunc cortex_a710_core_pwr_dwn 291 292cpu_reset_func_start cortex_a710 293 /* Disable speculative loads */ 294 msr SSBS, xzr 295 enable_mpmm 296cpu_reset_func_end cortex_a710 297 298 /* --------------------------------------------- 299 * This function provides Cortex-A710 specific 300 * register information for crash reporting. 301 * It needs to return with x6 pointing to 302 * a list of register names in ascii and 303 * x8 - x15 having values of registers to be 304 * reported. 305 * --------------------------------------------- 306 */ 307.section .rodata.cortex_a710_regs, "aS" 308cortex_a710_regs: /* The ascii list of register names to be reported */ 309 .asciz "cpuectlr_el1", "" 310 311func cortex_a710_cpu_reg_dump 312 adr x6, cortex_a710_regs 313 mrs x8, CORTEX_A710_CPUECTLR_EL1 314 ret 315endfunc cortex_a710_cpu_reg_dump 316 317declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 318 cortex_a710_reset_func, \ 319 cortex_a710_core_pwr_dwn 320