1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <common/debug.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gic.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/utils.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 18 #if USE_GIC_DRIVER != 3 19 #error "This file should only be used with USE_GIC_DRIVER=3" 20 #endif 21 22 #pragma weak gic_cpuif_enable 23 #pragma weak gic_cpuif_disable 24 25 /* The GICv3 driver only needs to be initialized in EL3 */ 26 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 27 28 /* List of zero terminated GICR frame addresses which CPUs will probe */ 29 static const uintptr_t *gicr_frames = NULL; 30 31 static const interrupt_prop_t arm_interrupt_props[] = { 32 #ifdef PLAT_ARM_G1S_IRQ_PROPS 33 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), 34 #endif 35 #ifdef PLAT_ARM_G0_IRQ_PROPS 36 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0), 37 #endif 38 #if ENABLE_FEAT_RAS && FFH_SUPPORT 39 INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0, 40 GIC_INTR_CFG_LEVEL) 41 #endif 42 }; 43 44 /* 45 * We save and restore the GICv3 context on system suspend. Allocate the 46 * data in the designated EL3 Secure carve-out memory. The `used` attribute 47 * is used to prevent the compiler from removing the gicv3 contexts. 48 */ 49 static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram") __used; 50 static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram") __used; 51 52 /* Define accessor function to get reference to the GICv3 context */ 53 DEFINE_LOAD_SYM_ADDR(rdist_ctx) 54 DEFINE_LOAD_SYM_ADDR(dist_ctx) 55 56 /* 57 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 58 * to core position. 59 * 60 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 61 * values read from GICR_TYPER don't have an MT field. To reuse the same 62 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 63 * that read from GICR_TYPER. 64 * 65 * Assumptions: 66 * 67 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 68 * - No CPUs implemented in the system use affinity level 3. 69 */ 70 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) 71 { 72 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 73 return plat_arm_calc_core_pos(mpidr); 74 } 75 76 gicv3_driver_data_t gic_data __unused = { 77 .gicd_base = PLAT_ARM_GICD_BASE, 78 /* unused for USE_GIC_DRIVER=3. Use gic_set_gicr_frames(), passing a ptr 79 * to an array with 2 values - the frame's base and a NULL pointer */ 80 .gicr_base = 0U, 81 .interrupt_props = arm_interrupt_props, 82 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), 83 .rdistif_num = PLATFORM_CORE_COUNT, 84 .rdistif_base_addrs = rdistif_base_addrs, 85 .mpidr_to_core_pos = arm_gicv3_mpidr_hash 86 }; 87 88 /* 89 * Initialises the gicr_frames array. It contains a NULL terminated list of 90 * non-contiguous blocks of GICR frames (located at uneven offsets). Most 91 * platforms will have one such block, except multichip configurations, which 92 * will usually have multiple. 93 */ 94 void gic_set_gicr_frames(const uintptr_t *plat_gicr_frames) 95 { 96 assert(plat_gicr_frames != NULL); 97 gicr_frames = plat_gicr_frames; 98 } 99 100 /****************************************************************************** 101 * ARM common helper to initialize the GIC. Only invoked by BL31 102 *****************************************************************************/ 103 void __init gic_init(unsigned int cpu_idx) 104 { 105 gicv3_driver_init(&gic_data); 106 gicv3_distif_init(); 107 } 108 109 /****************************************************************************** 110 * ARM common helper to enable the GIC CPU interface 111 *****************************************************************************/ 112 void gic_cpuif_enable(unsigned int cpu_idx) 113 { 114 gicv3_cpuif_enable(cpu_idx); 115 } 116 117 /****************************************************************************** 118 * ARM common helper to disable the GIC CPU interface 119 *****************************************************************************/ 120 void gic_cpuif_disable(unsigned int cpu_idx) 121 { 122 gicv3_cpuif_disable(cpu_idx); 123 } 124 125 /****************************************************************************** 126 * ARM common helper function to iterate over all GICR frames and discover the 127 * corresponding per-cpu redistributor frame as well as initialize the 128 * corresponding interface in GICv3. 129 *****************************************************************************/ 130 void gic_pcpu_init(unsigned int cpu_idx) 131 { 132 /* to guard against an empty array */ 133 int result = -1; 134 135 /* did the paltform initialise the array with gic_set_gicr_frames() */ 136 assert(gicr_frames != NULL); 137 138 do { 139 result = gicv3_rdistif_probe(*gicr_frames); 140 141 /* If the probe is successful, no need to proceed further */ 142 if (result == 0) 143 break; 144 145 gicr_frames++; 146 } while (*gicr_frames != 0U); 147 148 if (result == -1) { 149 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); 150 panic(); 151 } 152 gicv3_rdistif_init(cpu_idx); 153 } 154 155 /****************************************************************************** 156 * ARM common helpers to power GIC redistributor interface 157 *****************************************************************************/ 158 void gic_pcpu_off(unsigned int cpu_idx) 159 { 160 gicv3_rdistif_off(cpu_idx); 161 } 162 163 /****************************************************************************** 164 * Common helper to save & restore the GICv3 on resume from system suspend. It 165 * is the platform's responsibility to call these. 166 *****************************************************************************/ 167 void gic_save(void) 168 { 169 gicv3_redist_ctx_t * const rdist_context = 170 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx); 171 gicv3_dist_ctx_t * const dist_context = 172 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx); 173 174 /* 175 * If an ITS is available, save its context before 176 * the Redistributor using: 177 * gicv3_its_save_disable(gits_base, &its_ctx[i]) 178 * Additionally, an implementation-defined sequence may 179 * be required to save the whole ITS state. 180 */ 181 182 /* 183 * Save the GIC Redistributors and ITS contexts before the 184 * Distributor context. As we only handle SYSTEM SUSPEND API, 185 * we only need to save the context of the CPU that is issuing 186 * the SYSTEM SUSPEND call, i.e. the current CPU. 187 */ 188 gicv3_rdistif_save(plat_my_core_pos(), rdist_context); 189 190 /* Save the GIC Distributor context */ 191 gicv3_distif_save(dist_context); 192 193 /* 194 * From here, all the components of the GIC can be safely powered down 195 * as long as there is an alternate way to handle wakeup interrupt 196 * sources. 197 */ 198 } 199 200 void gic_resume(void) 201 { 202 const gicv3_redist_ctx_t *rdist_context = 203 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx); 204 const gicv3_dist_ctx_t *dist_context = 205 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx); 206 207 /* Restore the GIC Distributor context */ 208 gicv3_distif_init_restore(dist_context); 209 210 /* 211 * Restore the GIC Redistributor and ITS contexts after the 212 * Distributor context. As we only handle SYSTEM SUSPEND API, 213 * we only need to restore the context of the CPU that issued 214 * the SYSTEM SUSPEND call. 215 */ 216 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context); 217 218 /* 219 * If an ITS is available, restore its context after 220 * the Redistributor using: 221 * gicv3_its_restore(gits_base, &its_ctx[i]) 222 * An implementation-defined sequence may be required to 223 * restore the whole ITS state. The ITS must also be 224 * re-enabled after this sequence has been executed. 225 */ 226 } 227