1# 2# Copyright (c) 2016-2025, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33RESET_TO_BL2 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when RESET_TO_BL2 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include SVE registers in cpu context 67CTX_INCLUDE_SVE_REGS := 0 68 69# Debug build 70DEBUG := 0 71 72# By default disable authenticated decryption support. 73DECRYPTION_SUPPORT := none 74 75# Build platform 76DEFAULT_PLAT := fvp 77 78# Disable the generation of the binary image (ELF only). 79DISABLE_BIN_GENERATION := 0 80 81# Enable capability to disable authentication dynamically. Only meant for 82# development platforms. 83DYN_DISABLE_AUTH := 0 84 85# Enable the Maximum Power Mitigation Mechanism on supporting cores. 86ENABLE_MPMM := 0 87 88# Enable support for powerdown abandons 89FEAT_PABANDON := 0 90 91# Enable MPMM configuration via FCONF. 92ENABLE_MPMM_FCONF := 0 93 94# Flag to Enable Position Independant support (PIE) 95ENABLE_PIE := 0 96 97# Flag to enable Performance Measurement Framework 98ENABLE_PMF := 0 99 100# Flag to enable PSCI STATs functionality 101ENABLE_PSCI_STAT := 0 102 103# Flag to enable runtime instrumentation using PMF 104ENABLE_RUNTIME_INSTRUMENTATION := 0 105 106# Flag to enable stack corruption protection 107ENABLE_STACK_PROTECTOR := 0 108 109# Flag to enable exception handling in EL3 110EL3_EXCEPTION_HANDLING := 0 111 112# By default BL31 encryption disabled 113ENCRYPT_BL31 := 0 114 115# By default BL32 encryption disabled 116ENCRYPT_BL32 := 0 117 118# Default dummy firmware encryption key 119ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 120 121# Default dummy nonce for firmware encryption 122ENC_NONCE := 1234567890abcdef12345678 123 124# Build flag to treat usage of deprecated platform and framework APIs as error. 125ERROR_DEPRECATED := 0 126 127# Fault injection support 128FAULT_INJECTION_SUPPORT := 0 129 130# Flag to enable architectural features detection mechanism 131FEATURE_DETECTION := 0 132 133# Byte alignment that each component in FIP is aligned to 134FIP_ALIGN := 0 135 136# Default FIP file name 137FIP_NAME := fip.bin 138 139# Default FWU_FIP file name 140FWU_FIP_NAME := fwu_fip.bin 141 142# By default firmware encryption with SSK 143FW_ENC_STATUS := 0 144 145# For Chain of Trust 146GENERATE_COT := 0 147 148# Default number of 512 blocks per bitlock 149RME_GPT_BITLOCK_BLOCK := 1 150 151# Default maximum size of GPT contiguous block 152RME_GPT_MAX_BLOCK := 512 153 154# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 155# default, they are for Secure EL1. 156GICV2_G0_FOR_EL3 := 0 157 158# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 159# by lower ELs. 160HANDLE_EA_EL3_FIRST_NS := 0 161 162# Enable Handoff protocol using transfer lists 163TRANSFER_LIST := 0 164 165# Enable HOB list to generate boot information 166HOB_LIST := 0 167 168# Enables support for the gcc compiler option "-mharden-sls=all". 169# By default, disables all SLS hardening. 170HARDEN_SLS := 0 171 172# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 173# The default value is sha256. 174HASH_ALG := sha256 175 176# Whether system coherency is managed in hardware, without explicit software 177# operations. 178HW_ASSISTED_COHERENCY := 0 179 180# Flag to enable trapping of implementation defined sytem registers 181IMPDEF_SYSREG_TRAP := 0 182 183# Set the default algorithm for the generation of Trusted Board Boot keys 184KEY_ALG := rsa 185 186# Set the default key size in case KEY_ALG is rsa 187ifeq ($(KEY_ALG),rsa) 188KEY_SIZE := 2048 189endif 190 191# Option to build TF with Measured Boot support 192MEASURED_BOOT := 0 193 194# Option to enable the DICE Protection Environmnet as a Measured Boot backend 195DICE_PROTECTION_ENVIRONMENT :=0 196 197# NS timer register save and restore 198NS_TIMER_SWITCH := 0 199 200# Include lib/libc in the final image 201OVERRIDE_LIBC := 0 202 203# Build PL011 UART driver in minimal generic UART mode 204PL011_GENERIC_UART := 0 205 206# By default, consider that the platform's reset address is not programmable. 207# The platform Makefile is free to override this value. 208PROGRAMMABLE_RESET_ADDRESS := 0 209 210# Flag used to choose the power state format: Extended State-ID or Original 211PSCI_EXTENDED_STATE_ID := 0 212 213# Enable PSCI OS-initiated mode support 214PSCI_OS_INIT_MODE := 0 215 216# SMCCC_ARCH_FEATURE_AVAILABILITY support 217ARCH_FEATURE_AVAILABILITY := 0 218 219# By default, BL1 acts as the reset handler, not BL31 220RESET_TO_BL31 := 0 221 222# For Chain of Trust 223SAVE_KEYS := 0 224 225# Software Delegated Exception support 226SDEI_SUPPORT := 0 227 228# True Random Number firmware Interface support 229TRNG_SUPPORT := 0 230 231# Check to see if Errata ABI is supported 232ERRATA_ABI_SUPPORT := 0 233 234# Check to enable Errata ABI for platforms with non-arm interconnect 235ERRATA_NON_ARM_INTERCONNECT := 0 236 237# SMCCC PCI support 238SMC_PCI_SUPPORT := 0 239 240# Whether code and read-only data should be put on separate memory pages. The 241# platform Makefile is free to override this value. 242SEPARATE_CODE_AND_RODATA := 0 243 244# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 245# separate memory region, which may be discontiguous from the rest of BL31. 246SEPARATE_NOBITS_REGION := 0 247 248# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 249# region, platform Makefile is free to override this value. 250SEPARATE_BL2_NOLOAD_REGION := 0 251 252# Put RW DATA sections (.rwdata) in a separate memory region, which may be 253# discontiguous from the rest of BL31. 254SEPARATE_RWDATA_REGION := 0 255 256# Put SIMD context data structures in a separate memory region. Platforms 257# have the choice to put it outside of default BSS region of EL3 firmware. 258SEPARATE_SIMD_SECTION := 0 259 260# If the BL31 image initialisation code is recalimed after use for the secondary 261# cores stack 262RECLAIM_INIT_CODE := 0 263 264# SPD choice 265SPD := none 266 267# Enable the Management Mode (MM)-based Secure Partition Manager implementation 268SPM_MM := 0 269 270# Use the FF-A SPMC implementation in EL3. 271SPMC_AT_EL3 := 0 272 273# Enable SEL0 SP when SPMC is enabled at EL3 274SPMC_AT_EL3_SEL0_SP :=0 275 276# Use SPM at S-EL2 as a default config for SPMD 277SPMD_SPM_AT_SEL2 := 1 278 279# Flag to introduce an infinite loop in BL1 just before it exits into the next 280# image. This is meant to help debugging the post-BL2 phase. 281SPIN_ON_BL1_EXIT := 0 282 283# Flags to build TF with Trusted Boot support 284TRUSTED_BOARD_BOOT := 0 285 286# Build option to choose whether Trusted Firmware uses Coherent memory or not. 287USE_COHERENT_MEM := 1 288 289# Build option to add debugfs support 290USE_DEBUGFS := 0 291 292# Build option to fconf based io 293ARM_IO_IN_DTB := 0 294 295# Build option to support SDEI through fconf 296SDEI_IN_FCONF := 0 297 298# Build option to support Secure Interrupt descriptors through fconf 299SEC_INT_DESC_IN_FCONF := 0 300 301# Build option to choose whether Trusted Firmware uses library at ROM 302USE_ROMLIB := 0 303 304# Build option to choose whether the xlat tables of BL images can be read-only. 305# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 306# which is the per BL-image option that actually enables the read-only tables 307# API. The reason for having this additional option is to have a common high 308# level makefile where we can check for incompatible features/build options. 309ALLOW_RO_XLAT_TABLES := 0 310 311# Chain of trust. 312COT := tbbr 313 314# Use tbbr_oid.h instead of platform_oid.h 315USE_TBBR_DEFS := 1 316 317# Whether to enable D-Cache early during warm boot. This is usually 318# applicable for platforms wherein interconnect programming is not 319# required to enable cache coherency after warm reset (eg: single cluster 320# platforms). 321WARMBOOT_ENABLE_DCACHE_EARLY := 0 322 323# Default SVE vector length to maximum architected value 324SVE_VECTOR_LEN := 2048 325 326SANITIZE_UB := off 327 328# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 329# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 330# Default: disabled 331USE_SPINLOCK_CAS := 0 332 333# Enable Link Time Optimization 334ENABLE_LTO := 0 335 336# This option will include EL2 registers in cpu context save and restore during 337# EL2 firmware entry/exit. Internal flag not meant for direct setting. 338# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 339# CTX_INCLUDE_EL2_REGS. 340CTX_INCLUDE_EL2_REGS := 0 341 342# Enable Memory tag extension which is supported for architecture greater 343# than Armv8.5-A 344# By default it is set to "no" 345SUPPORT_STACK_MEMTAG := no 346 347# Select workaround for AT speculative behaviour. 348ERRATA_SPECULATIVE_AT := 0 349 350# select workaround for SME aborting powerdown 351ERRATA_SME_POWER_DOWN := 0 352 353# Trap RAS error record access from Non secure 354RAS_TRAP_NS_ERR_REC_ACCESS := 0 355 356# Build option to create cot descriptors using fconf 357COT_DESC_IN_DTB := 0 358 359# Build option to provide OpenSSL directory path 360OPENSSL_DIR := /usr 361 362# Select the openssl binary provided in OPENSSL_DIR variable 363ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 364 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 365else 366 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 367endif 368 369# Build option to use the SP804 timer instead of the generic one 370USE_SP804_TIMER := 0 371 372# Build option to define number of firmware banks, used in firmware update 373# metadata structure. 374NR_OF_FW_BANKS := 2 375 376# Build option to define number of images in firmware bank, used in firmware 377# update metadata structure. 378NR_OF_IMAGES_IN_FW_BANK := 1 379 380# Disable Firmware update support by default 381PSA_FWU_SUPPORT := 0 382 383# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 384# is enabled. 385ifeq ($(PSA_FWU_SUPPORT),1) 386PSA_FWU_METADATA_FW_STORE_DESC := 1 387else 388PSA_FWU_METADATA_FW_STORE_DESC := 0 389endif 390 391# Dynamic Root of Trust for Measurement support 392DRTM_SUPPORT := 0 393 394# Check platform if cache management operations should be performed. 395# Disabled by default. 396CONDITIONAL_CMO := 0 397 398# By default, disable SPMD Logical partitions 399ENABLE_SPMD_LP := 0 400 401# By default, disable PSA crypto (use MbedTLS legacy crypto API). 402PSA_CRYPTO := 0 403 404# getc() support from the console(s). 405# Disabled by default because it constitutes an attack vector into TF-A. It 406# should only be enabled if there is a use case for it. 407ENABLE_CONSOLE_GETC := 0 408 409# Build option to disable EL2 when it is not used. 410# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 411# functions must be enabled by platforms if they require it. 412# Disabled by default. 413INIT_UNUSED_NS_EL2 := 0 414 415# Disable including MPAM EL2 registers in context by default since currently 416# it's only enabled for NS world 417CTX_INCLUDE_MPAM_REGS := 0 418 419# Enable context memory usage reporting during BL31 setup. 420PLATFORM_REPORT_CTX_MEM_USE := 0 421 422# Enable early console 423EARLY_CONSOLE := 0 424 425# Allow platforms to save/restore DSU PMU registers over a power cycle. 426# Disabled by default and must be enabled by individual platforms. 427PRESERVE_DSU_PMU_REGS := 0 428 429# Enable RMMD to forward attestation requests from RMM to EL3. 430RMMD_ENABLE_EL3_TOKEN_SIGN := 0 431