1/* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <drivers/arm/gicv3.h> 12 13#include <platform_def.h> 14 15 .globl plat_arm_calc_core_pos 16 .globl plat_secondary_cold_boot_setup 17 .globl plat_is_my_cpu_primary 18 .globl platform_mem_init 19 .globl plat_my_core_pos 20 .globl plat_core_pos_by_mpidr 21 22 /* ----------------------------------------------------- 23 * void plat_secondary_cold_boot_setup (void); 24 * 25 * This function performs any platform specific actions 26 * needed for a secondary cpu after a cold reset e.g 27 * mark the cpu's presence, mechanism to place it in a 28 * holding pen etc. 29 * TODO: Should we read the PSYS register to make sure 30 * that the request has gone through. 31 * ----------------------------------------------------- 32 */ 33func plat_secondary_cold_boot_setup 34 mrs x0, mpidr_el1 35 36 /* 37 * There is no sane reason to come out of this wfi. This 38 * cpu will be powered on and reset by the cpu_on pm api 39 */ 40 dsb sy 41 bl plat_panic_handler 42endfunc plat_secondary_cold_boot_setup 43 44func plat_is_my_cpu_primary 45 mov x9, x30 46 bl plat_my_core_pos 47 cmp x0, #VERSAL_NET_PRIMARY_CPU 48 cset x0, eq 49 ret x9 50endfunc plat_is_my_cpu_primary 51 52 /* ----------------------------------------------------- 53 * unsigned int plat_my_core_pos(void) 54 * This function uses the plat_core_pos_by_mpidr() 55 * definition to get the index of the calling CPU. 56 * ----------------------------------------------------- 57 */ 58func plat_my_core_pos 59 mrs x0, mpidr_el1 60 b plat_core_pos_by_mpidr 61endfunc plat_my_core_pos 62 63/*---------------------------------------------------------------------- 64 * unsigned int platform_core_pos_by_mpidr(u_register_t mpid) 65 * 66 * Function to calculate the core position. 67 * 68 * clobbers: x0 - x3 69 * --------------------------------------------------------------------- 70 */ 71func plat_core_pos_by_mpidr 72 73 /* Extract individual affinity fields from MPIDR */ 74 ubfx x1, x0, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 75 ubfx x2, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 76 77 /* check if cpu_id valid */ 78 cmp x2, #PLATFORM_CORE_COUNT_PER_CLUSTER 79 b.hi error_invalid_core 80 81 /* check if cluster valid */ 82 cmp x1, #PLATFORM_CLUSTER_COUNT 83 b.hi error_invalid_cluster 84 85 /* core-position = cluster-id * cores per cluster + core-id */ 86 mov x3, #PLATFORM_CORE_COUNT_PER_CLUSTER 87 madd x0, x1, x3, x2 88 ret 89error_invalid_cluster: 90 mov x0, #E_INVALID_CLUSTER_COUNT 91 ret 92error_invalid_core: 93 mov x0, #E_INVALID_CORE_COUNT 94 ret 95endfunc plat_core_pos_by_mpidr 96 97 /* ----------------------------------------------------- 98 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 99 * This function uses the plat_core_pos_by_mpidr() 100 * definition to get the index of the calling CPU. 101 * ----------------------------------------------------- 102 */ 103func plat_arm_calc_core_pos 104 b plat_core_pos_by_mpidr 105endfunc plat_arm_calc_core_pos 106 107 /* --------------------------------------------------------------------- 108 * We don't need to carry out any memory initialization on Versal NET 109 * platform. The Secure RAM is accessible straight away. 110 * --------------------------------------------------------------------- 111 */ 112func platform_mem_init 113 ret 114endfunc platform_mem_init 115