1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <common/desc_image_load.h> 11 #include <drivers/arm/sp804_delay_timer.h> 12 #include <fvp_pas_def.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #if TRANSFER_LIST 16 #include <transfer_list.h> 17 #endif 18 19 #include <plat/arm/common/plat_arm.h> 20 #include <plat/common/platform.h> 21 #include <platform_def.h> 22 23 #include "fvp_private.h" 24 25 #if ENABLE_RME 26 /* 27 * The GPT library might modify the gpt regions structure to optimize 28 * the layout, so the array cannot be constant. 29 */ 30 static pas_region_t pas_regions[] = { 31 ARM_PAS_KERNEL, 32 ARM_PAS_SECURE, 33 ARM_PAS_REALM, 34 ARM_PAS_EL3_DRAM, 35 #ifdef ARM_PAS_GPTS 36 ARM_PAS_GPTS, 37 #endif 38 ARM_PAS_KERNEL_1, 39 ARM_PAS_PCI_MEM_1, 40 ARM_PAS_PCI_MEM_2 41 }; 42 43 static const arm_gpt_info_t arm_gpt_info = { 44 .pas_region_base = pas_regions, 45 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions), 46 .l0_base = ARM_L0_GPT_BASE, 47 .l1_base = ARM_L1_GPT_BASE, 48 .l0_size = ARM_L0_GPT_SIZE, 49 .l1_size = ARM_L1_GPT_SIZE, 50 .pps = GPCCR_PPS_1TB, 51 .pgs = GPCCR_PGS_4K 52 }; 53 #endif /* ENABLE_RME */ 54 55 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 56 { 57 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); 58 59 /* Initialize the platform config for future decision making */ 60 fvp_config_setup(); 61 } 62 63 void bl2_platform_setup(void) 64 { 65 arm_bl2_platform_setup(); 66 67 /* Initialize System level generic or SP804 timer */ 68 fvp_timer_init(); 69 } 70 71 #if ENABLE_RME 72 const arm_gpt_info_t *plat_arm_get_gpt_info(void) 73 { 74 return &arm_gpt_info; 75 } 76 #endif /* ENABLE_RME */ 77 78 /******************************************************************************* 79 * This function returns the list of executable images 80 ******************************************************************************/ 81 struct bl_params *plat_get_next_bl_params(void) 82 { 83 struct bl_params *arm_bl_params; 84 bl_mem_params_node_t *param_node __unused; 85 const struct dyn_cfg_dtb_info_t *fw_config_info __unused; 86 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 87 entry_point_info_t *ep __unused; 88 uint32_t next_exe_img_id __unused; 89 uintptr_t fw_config_base __unused; 90 91 arm_bl_params = arm_get_next_bl_params(); 92 93 #if __aarch64__ 94 /* Get BL31 image node */ 95 param_node = get_bl_mem_params_node(BL31_IMAGE_ID); 96 #else /* aarch32 */ 97 /* Get SP_MIN image node */ 98 param_node = get_bl_mem_params_node(BL32_IMAGE_ID); 99 #endif /* __aarch64__ */ 100 assert(param_node != NULL); 101 102 #if TRANSFER_LIST 103 arm_bl_params->head = ¶m_node->params_node_mem; 104 arm_bl_params->head->ep_info = ¶m_node->ep_info; 105 arm_bl_params->head->image_id = param_node->image_id; 106 107 arm_bl2_setup_next_ep_info(param_node); 108 #elif !RESET_TO_BL2 && !EL3_PAYLOAD_BASE 109 fw_config_base = 0UL; 110 111 /* Update the next image's ep info with the FW config address */ 112 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); 113 assert(fw_config_info != NULL); 114 115 fw_config_base = fw_config_info->config_addr; 116 assert(fw_config_base != 0UL); 117 118 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base; 119 #endif /* TRANSFER_LIST */ 120 121 return arm_bl_params; 122 } 123 124 int bl2_plat_handle_post_image_load(unsigned int image_id) 125 { 126 #if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST 127 if (image_id == HW_CONFIG_ID) { 128 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 129 struct transfer_list_entry *te __unused; 130 bl_mem_params_node_t *param_node __unused; 131 132 param_node = get_bl_mem_params_node(image_id); 133 assert(param_node != NULL); 134 135 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 136 assert(hw_config_info != NULL); 137 138 memcpy((void *)hw_config_info->secondary_config_addr, 139 (void *)hw_config_info->config_addr, 140 (size_t)param_node->image_info.image_size); 141 142 /* 143 * Ensure HW-config device tree is committed to memory, as the HW-Config 144 * might be used without cache and MMU enabled at BL33. 145 */ 146 flush_dcache_range(hw_config_info->secondary_config_addr, 147 param_node->image_info.image_size); 148 } 149 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/ 150 151 return arm_bl2_plat_handle_post_image_load(image_id); 152 } 153 154 uintptr_t plat_get_hw_dt_base(void) 155 { 156 const struct dyn_cfg_dtb_info_t *hw_config_info; 157 158 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 159 if (hw_config_info == NULL) { 160 return 0U; 161 } 162 163 return hw_config_info->secondary_config_addr; 164 } 165