1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 32workaround_reset_end neoverse_v3, CVE(2024, 5660) 33 34check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 35 36workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960 37#if IMAGE_BL31 38 /* 39 * The Neoverse V3 generic vectors are overridden to apply errata 40 * mitigation on exception entry from lower ELs. 41 */ 42 override_vector_table wa_cve_vbar_neoverse_v3 43 44#endif /* IMAGE_BL31 */ 45workaround_reset_end neoverse_v3, CVE(2022,23960) 46 47check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 48 49workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 50 /* --------------------------------- 51 * Sets BIT41 of CPUACTLR6_EL1 which 52 * disables L1 Data cache prefetcher 53 * --------------------------------- 54 */ 55 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 56workaround_reset_end neoverse_v3, CVE(2024, 7881) 57 58check_erratum_chosen neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 59 60 /* --------------------------------------------- 61 * HW will do the cache maintenance while powering down 62 * --------------------------------------------- 63 */ 64func neoverse_v3_core_pwr_dwn 65 /* --------------------------------------------- 66 * Enable CPU power down bit in power control register 67 * --------------------------------------------- 68 */ 69 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 70 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 71 72 isb 73 ret 74endfunc neoverse_v3_core_pwr_dwn 75 76cpu_reset_func_start neoverse_v3 77 /* Disable speculative loads */ 78 msr SSBS, xzr 79cpu_reset_func_end neoverse_v3 80 81 /* --------------------------------------------- 82 * This function provides Neoverse V3 specific 83 * register information for crash reporting. 84 * It needs to return with x6 pointing to 85 * a list of register names in ascii and 86 * x8 - x15 having values of registers to be 87 * reported. 88 * --------------------------------------------- 89 */ 90.section .rodata.neoverse_v3_regs, "aS" 91neoverse_v3_regs: /* The ascii list of register names to be reported */ 92 .asciz "cpuectlr_el1", "" 93 94func neoverse_v3_cpu_reg_dump 95 adr x6, neoverse_v3_regs 96 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 97 ret 98endfunc neoverse_v3_cpu_reg_dump 99 100declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 101 neoverse_v3_reset_func, \ 102 neoverse_v3_core_pwr_dwn 103 104declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \ 105 neoverse_v3_reset_func, \ 106 CPU_NO_EXTRA1_FUNC, \ 107 CPU_NO_EXTRA2_FUNC, \ 108 CPU_NO_EXTRA3_FUNC, \ 109 check_erratum_neoverse_v3_7881, \ 110 neoverse_v3_core_pwr_dwn 111