1# 2# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4# Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5# 6# SPDX-License-Identifier: BSD-3-Clause 7# 8include lib/xlat_tables_v2/xlat_tables.mk 9include lib/libfdt/libfdt.mk 10PLAT_INCLUDES := \ 11 -Iplat/intel/soc/agilex5/include/ \ 12 -Iplat/intel/soc/common/drivers/ \ 13 -Iplat/intel/soc/common/lib/sha/ \ 14 -Iplat/intel/soc/common/include/ 15 16# GIC-600 configuration 17GICV3_SUPPORT_GIC600 := 1 18# Include GICv3 driver files 19include drivers/arm/gic/v3/gicv3.mk 20AGX5_GICv3_SOURCES := \ 21 ${GICV3_SOURCES} \ 22 plat/common/plat_gicv3.c 23 24PLAT_BL_COMMON_SOURCES := \ 25 ${AGX5_GICv3_SOURCES} \ 26 common/fdt_wrappers.c \ 27 drivers/cadence/combo_phy/cdns_combo_phy.c \ 28 drivers/cadence/emmc/cdns_sdmmc.c \ 29 drivers/cadence/nand/cdns_nand.c \ 30 drivers/delay_timer/delay_timer.c \ 31 drivers/delay_timer/generic_delay_timer.c \ 32 drivers/ti/uart/aarch64/16550_console.S \ 33 plat/intel/soc/common/aarch64/platform_common.c \ 34 plat/intel/soc/common/aarch64/plat_helpers.S \ 35 plat/intel/soc/common/drivers/ccu/ncore_ccu.c \ 36 plat/intel/soc/common/drivers/combophy/combophy.c \ 37 plat/intel/soc/common/drivers/sdmmc/sdmmc.c \ 38 plat/intel/soc/common/drivers/ddr/ddr.c \ 39 plat/intel/soc/common/drivers/nand/nand.c \ 40 plat/intel/soc/common/lib/sha/sha.c \ 41 plat/intel/soc/common/lib/utils/alignment_utils.c \ 42 plat/intel/soc/common/socfpga_delay_timer.c \ 43 plat/intel/soc/common/socfpga_dt.c 44 45BL2_SOURCES += \ 46 common/desc_image_load.c \ 47 lib/xlat_tables_v2/aarch64/enable_mmu.S \ 48 lib/xlat_tables_v2/xlat_tables_context.c \ 49 lib/xlat_tables_v2/xlat_tables_core.c \ 50 lib/xlat_tables_v2/aarch64/xlat_tables_arch.c \ 51 lib/xlat_tables_v2/xlat_tables_utils.c \ 52 drivers/mmc/mmc.c \ 53 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ 54 drivers/io/io_storage.c \ 55 drivers/io/io_block.c \ 56 drivers/io/io_fip.c \ 57 drivers/io/io_mtd.c \ 58 drivers/partition/partition.c \ 59 drivers/partition/gpt.c \ 60 drivers/synopsys/emmc/dw_mmc.c \ 61 lib/cpus/aarch64/cortex_a55.S \ 62 lib/cpus/aarch64/cortex_a76.S \ 63 plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \ 64 plat/intel/soc/agilex5/soc/agilex5_memory_controller.c \ 65 plat/intel/soc/agilex5/soc/agilex5_mmc.c \ 66 plat/intel/soc/agilex5/soc/agilex5_pinmux.c \ 67 plat/intel/soc/agilex5/soc/agilex5_power_manager.c \ 68 plat/intel/soc/agilex5/soc/agilex5_ddr.c \ 69 plat/intel/soc/agilex5/soc/agilex5_iossm_mailbox.c \ 70 plat/intel/soc/common/bl2_plat_mem_params_desc.c \ 71 plat/intel/soc/common/socfpga_image_load.c \ 72 plat/intel/soc/common/socfpga_ros.c \ 73 plat/intel/soc/common/socfpga_storage.c \ 74 plat/intel/soc/common/socfpga_vab.c \ 75 plat/intel/soc/common/soc/socfpga_emac.c \ 76 plat/intel/soc/common/soc/socfpga_firewall.c \ 77 plat/intel/soc/common/soc/socfpga_handoff.c \ 78 plat/intel/soc/common/soc/socfpga_mailbox.c \ 79 plat/intel/soc/common/soc/socfpga_reset_manager.c \ 80 plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ 81 plat/intel/soc/agilex5/bl2_plat_setup.c \ 82 plat/intel/soc/common/drivers/wdt/watchdog.c 83 84include lib/zlib/zlib.mk 85PLAT_INCLUDES += -Ilib/zlib 86BL2_SOURCES += $(ZLIB_SOURCES) 87 88BL31_SOURCES += \ 89 drivers/arm/cci/cci.c \ 90 ${XLAT_TABLES_LIB_SRCS} \ 91 lib/cpus/aarch64/aem_generic.S \ 92 lib/cpus/aarch64/cortex_a55.S \ 93 lib/cpus/aarch64/cortex_a76.S \ 94 plat/common/plat_psci_common.c \ 95 plat/intel/soc/agilex5/bl31_plat_setup.c \ 96 plat/intel/soc/agilex5/soc/agilex5_cache.S \ 97 plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \ 98 plat/intel/soc/agilex5/soc/agilex5_power_manager.c \ 99 plat/intel/soc/common/socfpga_psci.c \ 100 plat/intel/soc/common/socfpga_sip_svc.c \ 101 plat/intel/soc/common/socfpga_sip_svc_v2.c \ 102 plat/intel/soc/common/socfpga_topology.c \ 103 plat/intel/soc/common/sip/socfpga_sip_ecc.c \ 104 plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 105 plat/intel/soc/common/soc/socfpga_mailbox.c \ 106 plat/intel/soc/common/soc/socfpga_system_manager.c \ 107 plat/intel/soc/common/soc/socfpga_reset_manager.c 108 109# Configs for A76 and A55 110HW_ASSISTED_COHERENCY := 1 111USE_COHERENT_MEM := 0 112CTX_INCLUDE_AARCH32_REGS := 0 113ERRATA_A55_1530923 := 1 114 115# Don't have the Linux kernel as a BL33 image by default 116ARM_LINUX_KERNEL_AS_BL33 := 0 117$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) 118$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) 119$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) 120 121# Configs for Boot Source 122SOCFPGA_BOOT_SOURCE_SDMMC ?= 0 123SOCFPGA_BOOT_SOURCE_QSPI ?= 0 124SOCFPGA_BOOT_SOURCE_NAND ?= 0 125 126$(eval $(call assert_booleans,\ 127 $(sort \ 128 SOCFPGA_BOOT_SOURCE_SDMMC \ 129 SOCFPGA_BOOT_SOURCE_QSPI \ 130 SOCFPGA_BOOT_SOURCE_NAND \ 131))) 132$(eval $(call add_defines,\ 133 $(sort \ 134 SOCFPGA_BOOT_SOURCE_SDMMC \ 135 SOCFPGA_BOOT_SOURCE_QSPI \ 136 SOCFPGA_BOOT_SOURCE_NAND \ 137))) 138 139# Configs for VAB Authentication 140SOCFPGA_SECURE_VAB_AUTH := 0 141$(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH)) 142$(eval $(call add_define,SOCFPGA_SECURE_VAB_AUTH)) 143 144PROGRAMMABLE_RESET_ADDRESS := 0 145RESET_TO_BL2 := 1 146BL2_INV_DCACHE := 0 147 148#To get the TF-A version via SMC calls 149DEFINES += -DVERSION_MAJOR=${VERSION_MAJOR} 150DEFINES += -DVERSION_MINOR=${VERSION_MINOR} 151DEFINES += -DVERSION_PATCH=${VERSION_PATCH} 152