1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <lib/mmio.h> 10 11 #include <mt_plat_spm_setting.h> 12 #include <mt_spm.h> 13 #include <mt_spm_cond.h> 14 #include <mt_spm_internal.h> 15 #include <mt_spm_reg.h> 16 #include <platform_def.h> 17 #include <pmic_wrap/inc/mt_spm_pmic_wrap.h> 18 19 #define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs) 20 #define MT_LP_TZ_MFG(ofs) (MFGSYS_BASE + 0xFA0000 + ofs) 21 22 /*********************************************************** 23 * Check pll idle condition 24 ***********************************************************/ 25 #define PLL_MFG MT_LP_TZ_MFG(0x008) 26 #define PLL_MFGSC MT_LP_TZ_MFG(0xC08) 27 28 /********************************************************** 29 * Check pll status other than idle condition 30 ***********************************************************/ 31 #define PLL_APLL1 MT_LP_TZ_APMIXEDSYS(0x404) 32 #define PLL_APLL2 MT_LP_TZ_APMIXEDSYS(0x418) 33 34 static struct plat_pll_cond_info pll_info[] = { 35 /* pll_addr, pll_mask, pll_bit_set */ 36 { PLL_MFG, 0x1, PLL_BIT_MFG }, 37 { PLL_MFGSC, 0x1, PLL_BIT_MFGSC }, 38 { PLL_APLL1, 0x1, PLL_BIT_APLL1 }, 39 { PLL_APLL2, 0x1, PLL_BIT_APLL2 }, 40 { 0, 0, PLL_BIT_MAX }, 41 }; 42 43 static struct plat_cond_info_t plat_cond_info = { 44 .pll_cond_table = pll_info, 45 }; 46 47 void plat_spm_cond_init(void) 48 { 49 register_plat_cond_info(&plat_cond_info); 50 } 51 52 /* 53 * BIT Operation 54 */ 55 #define _BIT_(_bit_) (uint32_t)(1 << (_bit_)) 56 #define _BITS_(_bits_, _val_) \ 57 ((((uint32_t) -1 >> (31 - ((1) ? _bits_))) & ~((1U << ((0) ? _bits_)) - 1)) &\ 58 ((_val_)<<((0) ? _bits_))) 59 #define _BITMASK_(_bits_) (((uint32_t) -1 >> (31 - ((1) ? _bits_))) &\ 60 ~((1U << ((0) ? _bits_)) - 1)) 61 #define _GET_BITS_VAL_(_bits_, _val_) (((_val_) & (_BITMASK_(_bits_))) >> ((0) ? _bits_)) 62 63 /* 64 * PMIC_WRAP 65 */ 66 #define VCORE_BASE_UV 40000 /* PMIC MT6365 */ 67 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) 68 #define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV) 69 70 #define NR_PMIC_WRAP_CMD (NR_IDX_ALL) 71 #define MAX_RETRY_COUNT (100) 72 #define SPM_DATA_SHIFT (16) 73 74 /* MT6365 */ 75 #define MT6365_BUCK_VCORE 0x17B2 76 #define MT6365_BUCK_VCORE_SRAM 0x15B4 77 #define MT6365_BUCK_VADSP_SRAM 0x204E 78 #define MT6365_BUCK_VADSP_SRAM_LOCK 0x03A8 79 #define MT6365_BUCK_O2_CON0 0x178A 80 #define MT6365_BUCK_O2_CON1 0x178C 81 #define MT6365_BUCK_O2_CON2 0x0456 82 #define MT6365_BUCK_VMDDR 0x1488 83 84 /* MT6319 */ 85 #define MT6319_BUCK_VDDQ_CON0 0x1442 86 #define MT6319_BUCK_VDDQ_CON1 0x1441 87 88 static struct pmic_wrap_cmd_setting cmd_table[NR_PMIC_WRAP_CMD] = { 89 { 90 (uint32_t)SPM_PWRAP_CMD0, 91 MT6365_BUCK_VCORE, 92 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(55000)), 93 }, /* 0.575 V */ 94 { 95 (uint32_t)SPM_PWRAP_CMD1, 96 MT6365_BUCK_VCORE, 97 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(60000)), 98 }, /* 0.600 V */ 99 { 100 (uint32_t)SPM_PWRAP_CMD2, 101 MT6365_BUCK_VCORE, 102 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(65000)), 103 }, /* 0.650 V */ 104 { 105 (uint32_t)SPM_PWRAP_CMD3, 106 MT6365_BUCK_VCORE, 107 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(72500)), 108 }, /* 0.725 V */ 109 { 110 (uint32_t)SPM_PWRAP_CMD4, 111 MT6365_BUCK_VCORE, 112 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(80000)), 113 }, /* 0.8 V */ 114 { 115 (uint32_t)SPM_PWRAP_CMD5, 116 MT6365_BUCK_VCORE_SRAM, 117 0x38, 118 }, /* VCORE_SRAM 0.75 V */ 119 { 120 (uint32_t)SPM_PWRAP_CMD6, 121 MT6365_BUCK_VCORE_SRAM, 122 0x40, 123 }, /* VCORE_SRAM 0.8 V */ 124 { 125 (uint32_t)SPM_PWRAP_CMD7, 126 MT6365_BUCK_VADSP_SRAM, 127 0x150, 128 }, /* VADSP_SRAM 0.75 V */ 129 { 130 (uint32_t)SPM_PWRAP_CMD8, 131 MT6365_BUCK_VADSP_SRAM, 132 0x200, 133 }, /* VADSP_SRAM 0.8 V */ 134 { 135 (uint32_t)SPM_PWRAP_CMD9, 136 MT6365_BUCK_O2_CON0, 137 0x2, 138 }, /* VCORE LP */ 139 { 140 (uint32_t)SPM_PWRAP_CMD10, 141 MT6365_BUCK_O2_CON1, 142 0x2, 143 }, /* VCORE NO_LP */ 144 { 145 (uint32_t)SPM_PWRAP_CMD11, 146 MT6365_BUCK_O2_CON2, 147 0x1, 148 }, /* NORMAL */ 149 { 150 (uint32_t)SPM_PWRAP_CMD12, 151 MT6365_BUCK_O2_CON2, 152 0x0, 153 }, /* SLEEP */ 154 { 155 (uint32_t)SPM_PWRAP_CMD13, 156 MT6319_BUCK_VDDQ_CON0, 157 0x8, 158 }, /* VDDQ OFF */ 159 { 160 (uint32_t)SPM_PWRAP_CMD14, 161 MT6319_BUCK_VDDQ_CON1, 162 0x8, 163 }, /* VDDQ ON */ 164 { 165 (uint32_t)SPM_PWRAP_CMD15, 166 MT6365_BUCK_VADSP_SRAM_LOCK, 167 0x9ca6, 168 }, /* unlock key */ 169 { 170 (uint32_t)SPM_PWRAP_CMD16, 171 MT6365_BUCK_VADSP_SRAM_LOCK, 172 0x0, 173 }, /* unlock key */ 174 { 175 (uint32_t)SPM_PWRAP_CMD17, 176 MT6365_BUCK_VMDDR, 177 0, 178 }, /* VMDDR off CMD */ 179 { 180 (uint32_t)SPM_PWRAP_CMD18, 181 MT6365_BUCK_VMDDR, 182 1, 183 }, /* VMDDR on CMD */ 184 { 185 (uint32_t)SPM_PWRAP_CMD19, 186 0, 187 0, 188 }, /* spare CMD */ 189 { 190 (uint32_t)SPM_PWRAP_CMD20, 191 MT6365_BUCK_VCORE, 192 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(55000)), 193 }, /* 0.575 V */ 194 { 195 (uint32_t)SPM_PWRAP_CMD21, 196 MT6365_BUCK_VCORE, 197 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(60000)), 198 }, /* 0.600 V */ 199 { 200 (uint32_t)SPM_PWRAP_CMD22, 201 MT6365_BUCK_VCORE, 202 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(65000)), 203 }, /* 0.650 V */ 204 { 205 (uint32_t)SPM_PWRAP_CMD23, 206 MT6365_BUCK_VCORE, 207 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(72500)), 208 }, /* 0.725 V */ 209 { 210 (uint32_t)SPM_PWRAP_CMD24, 211 MT6365_BUCK_VCORE, 212 _BITS_(7 : 0, VOLT_TO_PMIC_VAL(80000)), 213 }, /* 0. 8 V */ 214 }; 215 216 static struct pmic_wrap_phase_setting phase_table[NR_PMIC_WRAP_PHASE] = { 217 { 218 .cmd = cmd_table, 219 .nr_idx = NR_IDX_ALL, 220 }, 221 }; 222 223 static struct pmic_wrap_setting pmic_wrap_table = { 224 .phase = phase_table, 225 .phase_nr_idx = NR_PMIC_WRAP_PHASE, 226 }; 227 228 void plat_spm_pmic_wrap_init(void) 229 { 230 mt_spm_pmic_wrap_set_table(&pmic_wrap_table); 231 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); 232 } 233